Patent application number | Description | Published |
20100279234 | DOUBLE PATTERNING METHOD USING METALLIC COMPOUND MASK LAYER - A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer. | 11-04-2010 |
20120266810 | PLANARIZATION SYSTEM FOR HIGH WAFER TOPOGRAPHY - A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed. | 10-25-2012 |
20120270398 | PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY - A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed. | 10-25-2012 |
20120309197 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed. | 12-06-2012 |
20130154100 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art. | 06-20-2013 |
20130273740 | FILM PORTION AT WAFER EDGE - A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer. | 10-17-2013 |
20140035149 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm | 02-06-2014 |
20140272704 | THICKENING PHASE FOR SPIN COATING PROCESS - Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated. | 09-18-2014 |
20140272715 | Lithography Process on High Topology Features - A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist. | 09-18-2014 |