| Patent application number | Description | Published |
|---|
| 20080233745 | Interconnect Structures for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 09-25-2008 |
| 20080251928 | Carbonization of metal caps - An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring. | 10-16-2008 |
| 20090152722 | Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line comprises an alloying material; and forming an etch stop layer on the copper line. | 06-18-2009 |
| 20090275195 | Interconnect Structure Having a Silicide/Germanide Cap Layer - An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide. | 11-05-2009 |
| 20100059893 | Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line. | 03-11-2010 |
| 20100090342 | Metal Line Formation Through Silicon/Germanium Soaking - A method for forming interconnect structure includes providing a substrate; forming a low-k dielectric layer over the substrate; forming an opening in the low-k dielectric layer; after the step of forming the opening, performing a silicon/germanium soaking process to exposed surfaces of the low-k dielectric layer; and after the silicon/germanium soaking process, filling the opening. | 04-15-2010 |
| 20100090343 | Interconnect Structure for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 04-15-2010 |
| 20100295173 | Composite Underfill and Semiconductor Package - Embodiments of the invention exploit physical properties of nanostructures by using nanostructures in a composite underfill. An embodiment is a composite underfill comprising an epoxy matrix applied between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy matrix. Another embodiment is a semiconductor package comprising a semiconductor chip, a carrier, wherein the semiconductor chip is bonded to the carrier, and a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip. Further embodiments include a method for creating a semiconductor package comprising a composite underfill. | 11-25-2010 |
| 20110027991 | Interconnect Structure for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 02-03-2011 |
