Patent application number | Description | Published |
20090097327 | SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY - One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal. | 04-16-2009 |
20110037447 | Component Powered by HDMI Interface - A HDMI (High-Definition Multimedia Interface) transmitter component may be operated solely on power that is scavenged and converted from termination tail current received while the HDMI transmitter component is coupled to an HDMI compliant sink connector on a HDMI receiver component. The termination tail current is received at the transmitter component from a plurality of differential HDMI signals from terminators on a receiver component. A portion of the received tail current is converted to form a supply voltage Vdd source. Function logic on the transmitter component is operated using the Vdd voltage, and the function logic is configured to control the plurality of differential signals. | 02-17-2011 |
20110095794 | Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode - An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop. | 04-28-2011 |
20110261629 | Reduced Power Consumption in Retain-Till-Accessed Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells. | 10-27-2011 |
20110304994 | CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING - An integrated circuit structure includes a first conductive layer (MET | 12-15-2011 |
20120235716 | ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE - An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop. | 09-20-2012 |
20130033295 | CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS - Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal. | 02-07-2013 |
20140095919 | CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM - A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. | 04-03-2014 |
20140322867 | CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING - An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure ( | 10-30-2014 |