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| 20080206988 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions - A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate. | 08-28-2008 |
| 20080230815 | Mitigation of gate to contact capacitance in CMOS flow - Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics. | 09-25-2008 |
| 20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
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| 20090085524 | BATTERY CHARGING CIRCUIT - A circuit charges and maintains a battery. The circuit includes a microprocessor for receiving a current sense signal and a voltage sense signal. The microprocessor generates control signals for selectively operating the circuit in a charging mode and in a maintenance mode. The circuit includes a current sense circuit for measuring the battery's current consumption and generating the current sense signal responsive to the measured current consumption. The circuit includes a voltage sense circuit for measuring the battery's voltage and generating the voltage sense signal responsive to the measured battery voltage. The circuit includes a waveform generator circuit for receiving the control signals, and operating in response thereto to apply a charging signal to the battery when in the charging mode and to deactivate the charging signal when in the maintenance mode. The charging signal has an oscillating triangular waveform superimposed on a DC bias signal. | 04-02-2009 |
| 20090085525 | METHOD FOR CHARGING BATTERY - A method for charging a battery includes measuring the battery's voltage and comparing the battery voltage to a first threshold voltage. The method includes operating the battery in a charging mode if the measured battery voltage is less than the first threshold voltage, wherein operating in the charging mode comprises applying a charging signal to the battery. The charging signal has an oscillating triangular waveform superimposed on a DC bias signal. The method includes measuring the battery's current consumption and comparing the current consumption to a first threshold current. The method includes operating in a maintenance mode if the battery's current consumption is less than the first threshold current, wherein operating in the maintenance mode comprises terminating application of the charging signal to the battery. The method includes measuring, during operation in the maintenance mode, the battery's voltage and comparing the measured voltage to a second threshold voltage. The method includes applying the oscillating triangular waveform superimposed on the DC bias signal until the battery's voltage is equal to or greater than the second threshold voltage. | 04-02-2009 |
| 20090085526 | CIRCUIT FOR GENERATING TRIANGULAR WAVEFORM HAVING RELATIVELY SHORT LINEAR RISE TIME AND SUBSTANTIALLY LONG LINEAR FALL TIME - A circuit includes a pulse transformer having primary and secondary windings. An oscillating waveform is applied to the primary winding to induce an oscillating waveform at the secondary winding. A transistor in series with a first resistor is coupled between the secondary winding and the ground. An R-C network formed by a second and a third resistor and a capacitor is coupled to a base junction of the transistor. The R-C network causes a slow, tapered linear pinch off of the transistor's conductance to enable the circuit to output a triangular waveform, which is characterized by a relatively short linear rise time followed by a substantially long linear fall time. The R-C network is coupled to the secondary winding via a first and a second diode, respectively. | 04-02-2009 |
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| 20090051490 | METHODS AND SYSTEMS TO IMPROVE RFID INVENTORY POLLING ACCURACY - Methods, systems, and media to improve polling accuracy in RFID systems are disclosed. Embodiments comprise receiving information from one or more tags by a tag reader, comparing the information from the tags to other information, and adding the tag to an inventory if the tag does not exist in the other information. While some embodiments compare the tag information from the tags to baseline inventories for other areas, some embodiments compare it to current inventories for the other areas or compare it to a combination of both inventories. Some embodiments involve polling RFID tags in storage containers. Other embodiments involve machine-accessible mediums with instructions to receive information from the tag reader, analyze the information with baseline and current inventories of other areas, and store identification information for the tag in a current inventory database if the information is absent from the baseline and current inventories. | 02-26-2009 |
| 20090315677 | Container Manifest Integrity Maintenance System and Method - A system, method, and medium for tracking the contents of a container in which the items stored in the container are provided with radio frequency identification (“RFID”) tags, and a tracker affixed to the container periodically polls the items in the container to collect identification information. An electronic manifest, also attached to the container, is updated periodically to reflect items which have been added to the container or removed from the container since the last polling. The tracker emulates an RFID tag when polled by an external reader, responding by uploading the entire electronic manifest to the external reader. The external reader and the affixed reader preferably utilize distinct RFID protocols so as to produce a hierarchical manifest data structure with high integrity. | 12-24-2009 |
