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Huang, Zhubei City
Chiao-Chi Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110276730 | PACKET BASED DATA TRANSFER SYSTEM AND METHOD FOR HOST-SLAVE INTERFACE - In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host. | 11-10-2011 |
Chien-Hua Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120123745 | Adaptive Content-aware Aging Simulations - A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block. | 05-17-2012 |
Chien-Kai Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110285036 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 11-24-2011 |
Chih-Hsiang Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
| 20110193175 | LOWER PARASITIC CAPACITANCE FINFET - An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer. | 08-11-2011 |
Chun-Ju Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100044478 | NANOTIZATION OF MAGNESIUM-BASED HYDROGEN STORAGE MATERIAL - The invention utilizes a carbon nano material to nanotize a magnesium-based hydrogen storage material, thereby forming single or multiple crystals to enhance the surface to volume ratio and hydrogen diffusion channel of the magnesium-based hydrogen storage material. Therefore, the hydrogen storage material has higher hydrogen storage capability, higher absorption/desorption rate, and lower absorption/desorption temperature. | 02-25-2010 |
Chun-Yen Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100165665 | Power supply control circuit and method for sensing voltage in the power supply control circuit - The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit. | 07-01-2010 |
Juinn-Dar Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080198784 | Dynamical sequentially-controlled low-power multiplexer device - Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency. | 08-21-2008 |
| 20110153709 | DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS - A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture. | 06-23-2011 |
Ming-Chuan Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110019489 | Apparatus and method for data strobe and timing variation detection of an SDRAM interface - An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal. | 01-27-2011 |
| 20110302467 | Memory test system with advance features for completed memory system - In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands. | 12-08-2011 |
Ming-Tsung Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100278020 | Recording Method and Apparatus for Optical Disk Drive - A recording apparatus for an optical disk drive is provided. The recording apparatus includes a driver, a servo signal generator, a filter, and a counter. The driver controls a recording speed of the optical disk drive. The servo signal generator generates at least a servo signal. The filter with a specific bandwidth filters the servo signal to generate a filtered servo signal. The counter generate a count value according to the filtered servo signal and instructs the driver to decrease the recording speed of the optical disk drive when the count value exceeds a trigger value, so as to record with the decreased recording speed. | 11-04-2010 |
Pei-Cheng Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100079208 | Minimum pulse generation in a class-D amplifier - For minimum pulse generation in a class-D amplifier, a trapezoid switching waveform shape is used to replace the tradition triangle type to generate PWM pulses. Two voltages are compared with a sawtooth wave signal to generate the trapezoid waveform signal and a constant pulse width signal. An audio input signal is compared with the trapezoid waveform signal to generate a pulse width modulation signal, and either the pulse width modulation signal or the constant pulse width signal is used for driving a load at an output of the class-D amplifier. Flexible minimum pulse width could be obtained by offsetting one of the two voltages in generation of the constant pulse width signal. | 04-01-2010 |
Pei-Chung Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110043283 | VARIABLE FREQUENCY CLASS-D AMPLIFIER, CONTROL METHOD THEREOF, AND RAMP GENERATOR THEREFOR - A class-D amplifier includes a ramp generator to provide a ramp signal having a frequency varying with an audio input signal, and a modulator to convert the audio input signal to a pulse width modulation signal according to the ramp signal for a driver to drive a load device. The varying frequency of the ramp signal will cause the frequency of the pulse width modulation signal unfixed and consequently improves EMI issue. | 02-24-2011 |
Tsai Yu Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120126394 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer. | 05-24-2012 |
Yen-Chieh Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 03-08-2012 |
Yi-Ti Huang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100022211 | Low noise, highly linear amplifying stage and signal receiver using the same - The invention provides a signal amplifying stage, used in a signal receiver. The signal amplifying stage has: a fixed-gain low noise amplifier (LNA), amplifying an input signal; a variable-gain LNA (VG-LNA) array, amplifying the input signal, including a plurality of parallel VG-LNAs, the VG-LNA array being parallel with the fixed-gain LNA; a variable-gain amplifier (VGA), being in series with the fixed-gain LNA and the VG-LNA array, for amplifying output signals from the fixed-gain LNA and the VG-LNA array to generate an output signal; an attenuator, being in parallel with a combination of the fixed-gain LNA, the VG-LNA array and the VGA, for attenuating the input signal to generate the output signal; and a control loop, coupled to the VGA and the attenuator, for detecting power levels of the output signal to enable and control the fixed-gain LNA, the VG-LNA array, the VGA and the attenuator. | 01-28-2010 |