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Huang, Sunnyvale
An-Cheng Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100169567 | DYNAMIC DISK THROTTLING IN A WIDE AREA NETWORK OPTIMIZATION DEVICE - A network device may operate to increase application performance over a wide area network. In one particular implementation, the network device may monitor accesses to a disk drive from entities and determine whether an entity is accessing the disk drive in a manner that causes a disproportionate amount of performance degradation. If so, the network device may throttle access to the disk drive for the entity. | 07-01-2010 |
| 20100174823 | OPTIMIZING BATCH SIZE FOR PREFETCHING DATA OVER WIDE AREA NETWORKS - A data prefetching technique optimizes the batch size of prefetch requests. The optimized batch size may be determined based on a prefetch transfer time of a previous prefetch operation, where the prefetch transfer time is measured as an elapsed time interval from when data from the previous prefetch operation is first received to when the data from the previous prefetch operation is finished being received; | 07-08-2010 |
Chao-Ping Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080320418 | Graphical User Friendly Interface Keypad System For CAD - The present invention offers an improved GUI interface for CAD software to allow users easy access to menus. A user can execute commands and options with little disruption and with minimal hand movement. The keypad is represented on the computer screen and is called a GUFI (Graphical User Friendly Interface) keypad system. The keypad is a menu having a matrix of graphical buttons. A user selects a computer resource with a spatial input device and clicks the proper context button, the GUFI keypad displays only the functions or commands that pertain to the computer resource selected. The unique GUFI keypad system displays functions and commands in an arrayed, not in a pop-up or pull down menu, but in a pattern relating to the keys on the keyboard. Menu items are accessed through a one to one correspondence with the represented keys mapped to similar physically represented keys. | 12-25-2008 |
| 20110022976 | DYNAMIC USER INTERFACE SYSTEM - A user interface system for operating software on a computer includes a pointing device operable by a user's primary dexterous hand, a keyboard operable by the user's secondary dexterous hand, a matrix of keyboard keys on the keyboard. The matrix may include a first set of functions that are selected from a plurality of functions, and can be programmed to the matrix and displayed on the computer screen as a context menu. The selection of the functions being programmed to the matrix is dynamically linked to a previously executed function. | 01-27-2011 |
Chung-Kuang Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100289424 | Methods and Circuits for LED Drivers and for PWM Dimming Controls - The present invention relates to methods for LED driver applications, comprising the steps: providing an input voltage, V | 11-18-2010 |
Dajen Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100262945 | REPEATER DRIVEN ROUTING METHODOLOGY - A method for routing a chip, involving forming a plurality of nets configured to connect components of the chip, wherein each of the plurality of nets is included in a netlist, assigning at least one repeater to each of the plurality of nets in the netlist, wherein the repeaters are assigned prior to performing physical routing of the plurality of nets, inserting the at least one repeater in a corresponding net, wherein the insertion of the at least one repeater divides the corresponding net into at least two subnets, and performing the physical routing of the plurality of nets by connecting each of the subnets. | 10-14-2010 |
| 20100325600 | ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN - Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements. | 12-23-2010 |
Erica Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110145899 | Single Action Authentication via Mobile Devices - A method for authenticating a user includes receiving a user identification, confirming the user identification, sending a request to the user to perform a single action on a communication device, creating a session to receive the single action from the communication device, receiving an identifier from the communication device, using the identifier to verify that the user has the communication device, and authenticating the user based on the confirmed user information and the verification that the user has the communication device. The identification can include a username and a password or can be a one time password. | 06-16-2011 |
Fei Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090193018 | Matching Engine With Signature Generation - A system and a method generates at least one signature associated with document. In one embodiment, a document comprised of text is received and parsed to generate a token set. The token set includes a plurality of tokens. Each token corresponds to the text in the document that is separated by a predefined character characteristic. A score is calculated for each token in the token set based on a frequency and distribution of the text in the document. Each token is then ranked based on the calculated score. A subset of the ranked tokes is selected and a signature is generated for each occurrence of the selected tokens. The selected list of signatures is then output. | 07-30-2009 |
Guangsong Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100281533 | METHOD AND APPARATUS FOR IMPLEMENTING A LAYER 3/LAYER 7 FIREWALL IN AN L2 DEVICE - Methods and apparatus for transferring packets in a packet switched communication system. A system is provided that includes an L | 11-04-2010 |
Hang Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100254206 | Cache Optimizations Using Multiple Threshold Voltage Transistors - In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits. | 10-07-2010 |
| 20100329062 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 12-30-2010 |
Hui Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100094813 | REPRESENTING AND STORING AN OPTIMIZED FILE SYSTEM USING A SYSTEM OF SYMLINKS, HARDLINKS AND FILE ARCHIVES - A data de-duplication system is used with network attached storage and serves to reduce data duplication and file storage costs. Techniques utilizing both symlinks and hardlinks ensure efficient deletion file/data cleanup and avoid data loss in the event of crashes. | 04-15-2010 |
Jeff Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090164449 | SEARCH TECHNIQUES FOR CHAT CONTENT - Methods and apparatus are described for generating a searchable body of data representing a plurality of communications, and for facilitating searching of such a body of data. | 06-25-2009 |
Jianmin Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110010484 | OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY - During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages. | 01-13-2011 |
| 20110099460 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced. | 04-28-2011 |
| 20110149650 | Data Transfer Flows for On-Chip Folding - A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations. | 06-23-2011 |
| 20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING - A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die. | 06-23-2011 |
| 20110153913 | Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data - A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host. | 06-23-2011 |
Jonathan J. Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100079310 | ADAPTIVE KEYBOARD FOR ULTRA-MOBILE DEVICES - A method is provided. The method includes receiving inputs typed by a user of a keyboard and analyzing the inputs to identify typing errors made by the user. The method also includes customizing a layout of the keyboard to reduce the identified typing errors. | 04-01-2010 |
| 20100332668 | Multimodal proximity detection - Systems and methods for proximity detection between electronic devices are disclosed. One or more electronic devices transmit signals to a proximity server, which determines whether the first electronic device may be proximate the second electronic device. The proximity server transmits a signal to the first electronic device and the second device, and in response to the signal, the first and second electronic devices activate an environmental sensor, collect at least one sample of environmental data, extract at least one feature set of the environmental data, generate a first obscured feature from the feature set, transmit the first and second obscured feature sets to the proximity server. The proximity server uses the first obscured feature set and the second obscured feature set to determine whether the first electronic device and the second electronic device are proximate. | 12-30-2010 |
Lehan Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110088586 | Velocity control and terrain selection for gravity moderation - A system, method, and apparatus is described for providing a reduced or moderated gravity environment in a terrestrial payload. The system includes the evaluation of terrain to support an appropriately shaped vehicle guide, the construction of a vehicle guide, the provision of a high-speed vehicle and a control system adapted to control a motion of the vehicle across the vehicle guide with a specific velocity profile so as to produce a moderated gravity environment. | 04-21-2011 |
Qifan Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080309817 | COMBINED SCALING, FILTERING, AND SCAN CONVERSION - Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce the amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in a system-on-chip implementations. | 12-18-2008 |
| 20090268086 | METHOD AND SYSTEM FOR SCALING, FILTERING, SCAN CONVERSION, PANORAMIC SCALING, YC ADJUSTMENT, AND COLOR CONVERSION IN A DISPLAY CONTROLLER - Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations. | 10-29-2009 |
Qinping Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090070638 | METHOD AND SYSTEM FOR EXCEPTION DETECTING AND ALERTING - Methods and system for exception detecting and alerting are described. An exception indicating an occurrence of an error in an application and a path to the exception in an application space may be received. The received exception may be compared to a stored exception in a prior version of an exception data structure to determine whether the received exception is a new exception. The exception data structure may include a plurality of stored exceptions. The results of the comparison may be provided. | 03-12-2009 |
| 20090070733 | METHOD AND SYSTEM FOR PROBLEM NOTIFICATION AND PROCESSING - A notification of a problem associated with an application may be received. A difference may be determined between a problem version of the application and an operational version of the application to identify a change associated with the problem. A person associated with the change may be determined. A task of resolving the problem may be assigned to the person associated with the change. A person may be notified of the problem and of the assigning of the task based on the identified change. A modification may be performed to resolve the problem associated with the change based on the determining of the difference. | 03-12-2009 |
| 20110055640 | METHOD AND SYSTEM FOR EXCEPTION DETECTING AND ALERTING - Methods and system for exception detecting and alerting are described. An exception indicating an occurrence of an error in an application and a path to the exception in an application space may be received. The received exception may be compared to a stored exception in a prior version of an exception data structure to determine whether the received exception is a new exception. The exception data structure may include a plurality of stored exceptions. The results of the comparison may be provided. | 03-03-2011 |
Renxiang Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100017685 | ADAPTIVE ERROR CORRECTION - A transmitter generates error correction data according to an error correction scheme that logically arranges the communication data in a number of rows and a number of columns. The transmitter transmits the communication data and the error correction data. A receiver receives the communication data and the error correction data. The receiver processes the error correction data to correct errors in the communication data. The receiver generates information regarding the errors in the communication data. The transmitter processes the information to alter at the number of rows and/or the number of columns. | 01-21-2010 |
Shawn Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110088586 | Velocity control and terrain selection for gravity moderation - A system, method, and apparatus is described for providing a reduced or moderated gravity environment in a terrestrial payload. The system includes the evaluation of terrain to support an appropriately shaped vehicle guide, the construction of a vehicle guide, the provision of a high-speed vehicle and a control system adapted to control a motion of the vehicle across the vehicle guide with a specific velocity profile so as to produce a moderated gravity environment. | 04-21-2011 |
Victoria E. Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100021587 | VARIANTS OF BACILLUS sp. TS-23 ALPHA-AMYLASE WITH ALTERED PROPERTIES - Variants of | 01-28-2010 |
Weiqing Huang, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090254972 | Method and System for Implementing Changes to Security Policies in a Distributed Security System - Improved approaches for effectuating changes to security policies in a distributed security system are disclosed. The changes to security policies are distributed to those users (e.g., user and/or computers) in the security system that are affected. The distribution of such changes to security policies can be deferred for those affected users that are not activated (e.g., logged-in or on-line) with the security system. | 10-08-2009 |