Huang, Jhubei City
Chiang Hsia Huang, Jhubei City TW
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20120115546 | METHODS FOR INITIATING OPERATING VOLTAGES FOR SUBSCRIBER IDENTITY CARDS AND SYSTEMS UTILIZING THE SAME - A system for operating at least two subscriber identity cards has a subscriber identity module (SIM) controller generating a first voltage variable signal with a first voltage level to a first subscriber identity card during a first time period, generating the first voltage variable signal at a second voltage level to the first subscriber identity card during a second time period, receiving a first code indicating that generated voltage matches from the first subscriber identity card during the first or second time period, generating a first operating voltage with the first voltage level to the first subscriber identity card when receiving the first code in the first time period, generating the first operating voltage with the second voltage level when receiving the first code in the second time period. | 05-10-2012 |
Chih-Hao Huang, Jhubei City TW
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20110304006 | METHOD OF ALIGNMENT MARK PROTECTION AND SEMICONDUCTOR DEVICE FORMED THEREBY - A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate. | 12-15-2011 |
Chih-Kai Huang, Jhubei City TW
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20140028228 | CONTROL SYSTEMS AND METHODS FOR ANGLE ESTIMATION OF PERMANENT MAGNET MOTORS - An angle estimation control system of a permanent magnet motor is provided. The angle estimation control system includes a Clarke transform module, a Park transform module, and an angle estimation module. The Clarke transform module generates orthogonal current signals in accordance with motor phase currents. The Park transform module generates a current signal in response to the orthogonal current signals and an angle signal. The angle estimation module generates the angle signal in response to the current signal. The angle signal is related to a commutation angle of the permanent magnet motor. The current signal is controlled to be approximately equal to zero. The angle signal is further coupled to generate three phase motor voltage signals. | 01-30-2014 |
Chih Sheng Huang, Jhubei City TW
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20130118783 | CIRCUIT BOARD AND STORAGE DEVICE HAVING THE SAME - A circuit board includes a first pinout set of USB 2.0 standard provided on the circuit board; a second pinout set provided on the circuit board; and a flexible metal strip having a jut and four pinouts corresponding to StdA_SSRX−, StdA_SSRX+, StdA_SSTX−, and StdA_SSTX+ of USB 3.0 standard. | 05-16-2013 |
Chi-Hua Huang, Jhubei City TW
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20090202838 | SELF-ASSEMBLING OPTICAL FILM AND A METHOD OF MANUFACTURING THE SAME - A self-assembling optical film structure and a method of manufacturing the same are provided herein. The manufacturing method includes spreading a coating liquid formed with blending an acrylic resin, a fluothane-grafted acrylic resin, and a siloxane-grafted acrylic resin, or the liquid can be formed with an acrylic resin containing a fluorine compound or a silicon compound, so as to form a self-assembling optical film structure on a coated film surface, thus significantly reducing the cost. As a result, random and irregular array is generated during spreading the coating liquid, so we can effectively reduce the generation of optical interference due to the regular structure, and the product thereby has better brightness enhancement property and can be composed of relatively less layers of optical films. | 08-13-2009 |
Chu Huang, Jhubei City TW
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20100237509 | IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING - An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving. | 09-23-2010 |
Chun-Lung Huang, Jhubei City TW
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20090328142 | Systems and Methods for Webpage Verification Using Data-Hiding Technology - A system for webpage verification comprises an authentication module configured to authenticate a user identifier if the user identifier is unique in the system, the user identifier being related to the identity of a user, a data-hiding module configured to generate a first data-hidden object based on a unique user identifier, at least one webpage identifier and a base object in accordance with a data-hiding algorithm, each of the at least one webpage identifiers being related to the identity of one of at least one webpage of the user, a memory module to store at least one of the said user identifier, the at least one webpage identifier, the base object, and the required parameters of data-hiding algorithm, and a verification module configured to retrieve the first data-hidden object from one of the at least one webpage based on one of the at least one webpage identifier, retrieve a user identifier and all of the webpage identifiers from the memory module based on the one webpage identifier, generate a second data-hidden object based on the retrieved webpage identifiers, the retrieved user identifier and the base object, and compare the first data-hidden object with the second data-hidden object. | 12-31-2009 |
Chun-Yen Huang, Jhubei City TW
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20090195221 | Capacitor charger with a modulated current varying with an input voltage and method thereof - In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery. | 08-06-2009 |
Eric Huang, Jhubei City TW
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20090001462 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 01-01-2009 |
20110163376 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type. | 07-07-2011 |
20120003803 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 01-05-2012 |
20140197488 | METHOD OF FORMING HIGH VOLTAGE DEVICE - A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type. | 07-17-2014 |
20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 09-04-2014 |
Hsin-Chiang Huang, Jhubei City TW
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20090284445 | LED DATA INPUT SCHEME WITH SEQUENTIAL SCAN METHOD AND CASCADE CONNECTION FOR LIGHT EMITTING DIODE (LED) DISPLAY SYSTEM - This invention is an architecture of Driver IC used by the LED light systems. Each Driver IC comprises at least one Drive Cell that connects to an individual LED. The LED data are transmitted via a sequential scanning method from Drive Cell to Drive Cell, and from Driver IC to Driver IC that are connected in a cascade manner. | 11-19-2009 |
Huan-Tsung Huang, Jhubei City TW
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20100065925 | LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension. | 03-18-2010 |
20100078733 | TRANSISTOR PERFORMANCE IMPROVING METHOD WITH METAL GATE - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode. | 04-01-2010 |
20120003804 | Local Charge and Work Function Engineering on MOSFET - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension. | 01-05-2012 |
Jia-Chi Huang, Jhubei City TW
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20090167993 | METHOD FOR FORMING OPTICAL COMPENSATING FILMS, OPTICAL COMPENSATING FILMS FORMED THEREBY, STRUCTURE OF OPTICAL COMPENSATING FILMS, AND POLARIZING PLATES - The invention provides a method for forming optical compensating films, including: (a) providing a suspension containing clay; (b) adding a mono-functional acrylic oligomer of formula (I) in the suspension, wherein n | 07-02-2009 |
20090279176 | ANTIGLARE FILM AND MANUFACTURING METHOD THEREOF - The invention provides an antiglare film. A resin layer is disposed on a substrate. Micro-aggregates are distributed in an interior and over a surface of the resin layer. Each of the micro aggregates has a size of 0.1-3 μm and is formed by aggregating aggregated nano-particles. The micro-aggregates distributing over the surface result in a surface roughness of the resin layer. The weight ratio of the resin layer to the micro-aggregates is 1:0.1-0.7. | 11-12-2009 |
Kun-Jen Huang, Jhubei City TW
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20130200161 | ELECTRONIC TAG CAPABLE OF COUPLING TO METAL - An electronic tag capable of coupling to metal can be attached to the metallic surface of a product, and includes a substrate, a radiation body arranged on a surface of the substrate, a grounding body and a reference line. The grounding body is also arranged on the aforementioned surface and electrically connects to the radiation body. The reference line is arranged on the aforementioned surface and in the grounding body. While such electronic tag is attached to the metallic surface of a product, a portion of the grounding body, which is opposite to the radiation body, contacts with such metallic surface, so that the signal reading distance of such electronic tag can be broadened and extended in virtue of coupling such grounding body with such metallic surface to cause the grounding area to be enlarged. The extent of such contact shall not extend beyond such reference line. | 08-08-2013 |
Kuo Bin Huang, Jhubei City TW
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20110086504 | METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed. | 04-14-2011 |
20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
20120086075 | DEVICE WITH ALUMINUM SURFACE PROTECTION - A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer. | 04-12-2012 |
20130078809 | SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS - A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture. | 03-28-2013 |
20130130488 | Method of Patterning a Metal Gate of Semiconductor Device - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 05-23-2013 |
20130143406 | TECHNIQUES PROVIDING PHOTORESIST REMOVAL - A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone. | 06-06-2013 |
20130267099 | CHEMICAL DISPENSING SYSTEM AND METHOD - A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer. | 10-10-2013 |
20150206755 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 07-23-2015 |
Ming Chuan Huang, Jhubei City TW
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20100153636 | CONTROL SYSTEM AND METHOD FOR MEMORY ACCESS - A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data. | 06-17-2010 |
Ming-Feng Huang, Jhubei City TW
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20100066465 | DOWN CONVERSION FILTER - A down conversion filter with a plurality of sampling capacitor, wherein at least one sampling capacitor is discharged in sampling phases or charge-summing phases of the other sampling capacitors. | 03-18-2010 |
20100130146 | DOWN CONVERSION FILTER AND COMMUNICATION RECEIVING APPARATUS - A down-conversion filter is provided, using first and second input terminals to receive signals that are differentially outputted by a preceding circuit, and using an output terminal to output a down-converted and filtered signal. An output capacitor is coupled to the output terminal. A first switched-capacitor network is arranged between the first input terminal and the output terminal. A second switched-capacitor network is arranged between the second input terminal and the output terminal. Each switched-capacitor network has capacitors, charging switches and charge-summing switches. The charging switches are designed to alternatively couple the capacitors to the first (or second) input terminal. The charge-summing switches are designed to couple the capacitors to the output terminal. | 05-27-2010 |
20110248768 | CHARGE DOMAIN FILTER WITH CONTROLLABLE TRANSFER FUNCTIONS AND TRANSFER FUNCTION CONTROL METHODS THEREOF - A charge domain filter with controllable transfer function is disclosed. The charge domain filter has a plurality of switched-capacitor networks, a switching device and a current adder. The switched-capacitor networks are interleaving controlled, and each have an input terminal and an output terminal, and the input terminals of all of the switched-capacitor networks are connected together to be coupled to an input signal. The switching device is designed for transfer function control, and is operated according to a switch control signal. The switching device determines connections between the output terminals of the switched-capacitor networks and how the output terminals of the switched-capacitor networks are coupled to the current adder and thereby generates at least one current adder input. The at least one current adder input is received by the current adder, and the current adder outputs an output signal accordingly. | 10-13-2011 |
Pei-Cheng Huang, Jhubei City TW
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20090080676 | Driver circuit and driving method for electrostatic loudspeaker - The present invention discloses a driver circuit for an electrostatic loudspeaker, comprising: a digital modulation encoder for receiving a digital audio signal and a fixed frequency pulse signal, and mixing them by modulation; a digital to analog converter for converting the output of the digital modulation encoder to an analog signal; a transformer for adjusting the voltage amplitude of the analog signal; and a demodulator for demodulating the adjusted analog signal to driver a speaker. | 03-26-2009 |
20100066266 | Led bulb, light emitting device control method, and light emitting device controller circuit with dimming function adjustable by AC signal - The present invention discloses a light emitting device control method for adjusting the brightness of the light emitting device by an AC signal, comprising: receiving a signal having a turn ON angle and converting the signal to a DC signal; obtaining an average of the DC signal level, the average being a function of the turn ON angle; determining a reference voltage of a current source circuit according to the average of the DC signal level; and controlling a current flow through the light emitting device by the current source circuit. | 03-18-2010 |
Sheng-Yung Huang, Jhubei City TW
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20110296076 | HYBRID DATA TRANSMISSION EXCHANGER AND HYBRID DATA TRANSMISSION METHOD - The present invention discloses a hybrid data transmission exchanger and a hybrid data transmission method, whereby hosts can access storage units and share data. The hybrid data transmission exchanger comprises an embedded central processing unit, a virtual bridge/switch unit, an optical fiber network connection unit and an Ethernet connection unit. The embedded central processing unit is connected with the storage units and detects the virtual bridge/switch unit, optical fiber network connection unit and Ethernet connection unit to detect the connection states of a host. A host can directly access the storage units via the optical fiber network connection unit or the Ethernet connection unit. When a host is linked to the exchanger via a PCIe interface, the virtual bridge/switch unit converts an address area and a request identification code of the host to correspond to the embedded central processing unit, whereby the host can access storage units. | 12-01-2011 |
Shen-Yu Huang, Jhubei City TW
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20130140905 | ISOLATION CELL - An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage. | 06-06-2013 |
Shih-Fen Huang, Jhubei City TW
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20150311140 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar. | 10-29-2015 |
Ting-Li Huang, Jhubei City TW
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20080313601 | Speech IC Simulation Method, System and Medium thereof - In a speech IC simulation method, a system, a medium and a firmware code generation method, the speech IC simulation method for obtaining a simulation result of a speech IC project includes the steps of establishing and compiling a speech IC project in a wizard interface, setting and displaying a visualized in-circuit emulator (ICE) allocation interactively corresponding to the speech IC project in a visualized allocation interface, and setting and performing the clips and corresponsive system trigger events in a visualized clip editing and event setting interface if a modification of the speech IC project is required. Moreover, the firmware code from compiling the speech IC project may be outputted through an output port such as an USB port or a printer port or recorded in a memory of a circuit emulator. | 12-18-2008 |
Tong-Yuh Huang, Jhubei City TW
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20100243442 | ELECTROCHEMICAL SENSING TEST PIECE WITHOUT HEMOCYTE INTERFERENCE - The present invention provides an electrochemical sensing test piece without hemocyte interference, including a main body, electrode unit, reaction tank and chemical reaction zone. The detection zone of the electrode unit corresponds to the inserting end of the main body, and the reaction zone of the electrode unit corresponds to the sensing end of the main body. The reaction tank is arranged onto the sensing end correspondingly to the reaction zone of the electrode unit. The reaction tank is provided with a porous filter layer, whose aperture must be less than 6 μm for or separation of hemocyte in the blood sample. A chemical reaction zone is arranged between the porous filter layer and the reaction zone of the electrode unit. The hemocyte of the blood sample can be blocked and filtered by the porous filter layer, ensuring that the serum of blood sample can enter into the chemical reaction zone. | 09-30-2010 |
Tsung-Cheng Huang, Jhubei City TW
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20080299769 | SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS - A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film. | 12-04-2008 |
20100273286 | Method Of Fabricating An Integrated CMOS-MEMS Device - An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure. | 10-28-2010 |
20140267692 | AUTOMATED WAFER INSPECTION - In semiconductor fabrication processes, one or more wafers are often exposed to processes such as chemical vapor deposition to form semiconductor components thereupon. Often, some of the wafers exhibit flaws due to contamination or processing errors occurring before, during, or after component formation. Inspection of the wafers is often performed by direct visual inspection of humans, which is prone to errors due to flaws that are too small to view directly; to particles naturally arising in the human eye; and to fatigue caused by inspection of large numbers of wafers. Presented herein are inspection techniques involving positioning the wafer in a dark chamber exposing the surface of the wafer to a light source at a first angle, and capturing with a camera an image of the light source reflected from the surface of the wafer at a second angle. Wafers identified as exhibiting flaws are removed from the wafer set. | 09-18-2014 |
20150079806 | Photoresist Coating Scheme - A method includes rotating a wafer at a first speed for a first time duration. The wafer is rotated at a second speed that is lower than the first speed for a second time duration after the first time duration. The wafer is rotated at a third speed that is higher than the second speed for a third time duration after the second time duration. A photoresist is dispensed on the wafer during the first time duration and at least a portion of a time interval that includes the second time duration and the third time duration. | 03-19-2015 |
Yin Chin Huang, Jhubei City TW
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20120020164 | TEST METHOD FOR SCREENING MANUFACTURING DEFECTS IN A MEMORY ARRAY - A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell at an intersection of the program conductive line and a conductive line extending in a second direction to a selected high value, and determining whether a cell initially at a low value and associated with a conductive line extending in the first direction and adjacent to the program conductive line is disturbed. | 01-26-2012 |
Yu-Lien Huang, Jhubei City TW
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20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 12-18-2008 |
20110006390 | STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME - A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench. | 01-13-2011 |
20110269287 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin. | 11-03-2011 |
20120018848 | HIGH SURFACE DOPANT CONCENTRATION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer. | 01-26-2012 |
20120070953 | METHOD OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical. | 03-22-2012 |
20120112248 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures. | 05-10-2012 |
20120187524 | DOPED OXIDE FOR SHALLOW TRENCH ISOLATION (STI) - The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD | 07-26-2012 |
20120190167 | MECHANISMS OF DOPING OXIDE FOR FORMING SHALLOW TRENCH ISOLATION - The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology. | 07-26-2012 |
20120248550 | PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD | 10-04-2012 |
20120315733 | METHOD OF FABRICATING GATE ELCTRODE USING A TREATED HARD MASK - A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure. | 12-13-2012 |
20130017678 | METHODS OF ANNEAL AFTER DEPOSITION OF GATE LAYERSAANM TSAI; Chun HsiungAACI Xinpu TownshipAACO TWAAGP TSAI; Chun Hsiung Xinpu Township TWAANM YU; Xiong-FeiAACI HsinchuAACO TWAAGP YU; Xiong-Fei Hsinchu TWAANM HUANG; Yu-LienAACI Jhubei CityAACO TWAAGP HUANG; Yu-Lien Jhubei City TWAANM LIN; Da-WenAACI Hsinchu CityAACO TWAAGP LIN; Da-Wen Hsinchu City TW - Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer. | 01-17-2013 |
20130037863 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures. | 02-14-2013 |
20130228871 | PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer. | 09-05-2013 |
20130270628 | Replacement Channels - The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure. | 10-17-2013 |
20130334605 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - A fin field-effect transistor (FinFET) includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region uniformly beneath a top surface and sidewall surfaces of the fin structure, the LDD region having a depth less than about 25 nm. Another FinFET includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region, and a top surface of the fin structure has a different crystal structure from a sidewall surface of the fin structure. A method of making a FinFET includes forming a fin structure on a substrate. The method further includes performing a pulsed plasma doping on the fin structure to form lightly doped drain (LDD) regions in the fin structure. | 12-19-2013 |
20140048855 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance. | 02-20-2014 |
20140084351 | REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST - A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material. | 03-27-2014 |
20140117456 | Semiconductor Device and Fabrication Method Thereof - A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance. | 05-01-2014 |
20140120693 | METHOD OF MAKING A SHALLOW TRENCH ISOLATION (STI) STRUCTURES - A method of making shallow trench isolation (STI) structures includes forming a first opening in a substrate and filling the first opening with silicon oxide to form a first STI structure. The method further includes doping a top surface of the silicon oxide with carbon, wherein a bottom portion of the silicon oxide is free of carbon. The method further includes planarizing the silicon oxide so that the top surface of the silicon oxide is at substantially a same level as a surface of the substrate surrounding the silicon oxide. | 05-01-2014 |
20140127893 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance. | 05-08-2014 |
20140145242 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 05-29-2014 |
20140191333 | METHOD OF PROTECTING AN INTERLAYER DIELECTRIC LAYER AND STRUCTURE FORMED THEREBY - This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures. | 07-10-2014 |
20140203333 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal. | 07-24-2014 |
20140239354 | FinFETs and Methods for Forming the Same - A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric. | 08-28-2014 |
20140239404 | FInFET Structure and Method for Forming the Same - A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process. | 08-28-2014 |
20140252431 | Semiconductor Device Structure and Method of Forming Same - An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL. | 09-11-2014 |
20140252432 | Semiconductor Device and Method for Forming the Same - A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer. | 09-11-2014 |
20140256113 | Semiconductor Device and Method for Forming the Same - A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer. A top portion of the capping layer is then removed, while leaving a bottom portion of the capping layer over the dielectric layer. A gate structure is then formed over the remaining capping layer. | 09-11-2014 |
20140264442 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefore, to enhance carrier mobility and upgrade the device performance. | 09-18-2014 |
20140319462 | BUFFER LAYER OMEGA GATE - A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions. | 10-30-2014 |
20140327046 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 11-06-2014 |
20140335685 | METHODS OF ANNEALING AFTER DEPOSITION OF GATE LAYERS - A method of fabricating a gate structure includes depositing a high dielectric constant (high-k) dielectric layer over a substrate. The method further includes performing a multi-stage preheat high-temperature anneal. Performing the multi-stage preheat high-temperature anneal includes performing a first stage preheat at a temperature in a range from about 400° C. to about 600° C., performing a second stage preheat at a temperature in a range from about 700° C. to about 900° C., and performing a high temperature anneal at a peak temperature in a range from 875° C. to about 1200° C. | 11-13-2014 |
20140342537 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure. Performing the plasma doping process includes implanting plasma ions into the fin structures at a plurality of implant angles, and the plurality of implant angles has an angular distribution and at least one highest angle frequency value. | 11-20-2014 |
20140361336 | Fin Structure of Semiconductor Device - The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. | 12-11-2014 |
20140367800 | SEMICONDUCTOR DEVICE WITH STRAIN TECHNIQUE - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a fin structure disposed over the substrate in the gate region. The fin structure includes a first semiconductor material layer as a lower portion of the fin structure, a semiconductor oxide layer as a middle portion of the fin structure and a second semiconductor material layer as an upper portion of the fin structure. The semiconductor device also includes a dielectric feature disposed between two adjacent fin structures over the substrate. A top surface of the dielectric feature located, in a horizontal level, higher than the semiconductor oxide layer with a distance d. The semiconductor device also includes a high-k (HK)/metal gate (MG) stack disposed in the gate region, including wrapping over a portion of the fin structure. | 12-18-2014 |
20150137266 | REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST - A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material. | 05-21-2015 |
20150155370 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - A method of doping a FinFET includes forming a semiconductor fin on a substrate, the substrate having a first device region and a second device region. The semiconductor fin is formed on a surface of the substrate in the second device region and has a top surface and sidewalls. The first device region is covered with a hard mask and the semiconductor fin and the hard mask are exposed to a deposition process to form a dopant-rich layer having an n-type or p-type dopant on the top surface and the sidewalls of the semiconductor fin. The dopant from the dopant-rich layer is diffused into the semiconductor fin by performing an annealing process in which the first device region is free of diffusion of the diffused dopant or another dopant from the hard mask. | 06-04-2015 |
20150187571 | Germanium-Containing FinFET and Methods for Forming the Same - A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched. | 07-02-2015 |
20150270401 | Combination FinFET and Methods of Forming Same - An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials. | 09-24-2015 |
20150279840 | FINFETS WITH LOW SOURCE/DRAIN CONTACT RESISTANCE - An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion. | 10-01-2015 |
20150295089 | FINFETS WITH CONTACT-ALL-AROUND - An integrated circuit structure includes a semiconductor substrate, a semiconductor fin over the semiconductor substrate, a gate stack on a top surface and a sidewall of the semiconductor fin, a source/drain region on a side of the gate stack, and a contact plug encircling a portion of the source/drain region. | 10-15-2015 |
20150311111 | Fin Structure of Semiconductor Device - The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. | 10-29-2015 |
Yung-Chi Huang, Jhubei City TW
Patent application number | Description | Published |
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20100328947 | LIGHT-EMITTING DIODE LIGHT SOURCE ASSEMBLY WITH HEAT DISSIPATION BASE - A light-emitting diode (LED) light source assembly with a heat dissipation base is provided. The LED light source assembly includes the heat dissipation base and a light bar. The light bar includes a flexible printed circuit (FPC) board and at least one LED unit which is disposed on the FPC board and electrically connected to the FPC board. The heat dissipation base has two retaining recesses for lodging the side portions of the FPC board, so the FPC board can be thermally conductively connected to the heat dissipation base. Because of the flexibility of the FPC board, it is easy to lodge the FPC board in the heat dissipation base via the retaining recesses. Thus, the cost for arranging the light bar can be economized. | 12-30-2010 |