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Huang, Jhubei City
Chiang Hsia Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120115546 | METHODS FOR INITIATING OPERATING VOLTAGES FOR SUBSCRIBER IDENTITY CARDS AND SYSTEMS UTILIZING THE SAME - A system for operating at least two subscriber identity cards has a subscriber identity module (SIM) controller generating a first voltage variable signal with a first voltage level to a first subscriber identity card during a first time period, generating the first voltage variable signal at a second voltage level to the first subscriber identity card during a second time period, receiving a first code indicating that generated voltage matches from the first subscriber identity card during the first or second time period, generating a first operating voltage with the first voltage level to the first subscriber identity card when receiving the first code in the first time period, generating the first operating voltage with the second voltage level when receiving the first code in the second time period. | 05-10-2012 |
Chih-Hao Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110304006 | METHOD OF ALIGNMENT MARK PROTECTION AND SEMICONDUCTOR DEVICE FORMED THEREBY - A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate. | 12-15-2011 |
Chi-Hua Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090202838 | SELF-ASSEMBLING OPTICAL FILM AND A METHOD OF MANUFACTURING THE SAME - A self-assembling optical film structure and a method of manufacturing the same are provided herein. The manufacturing method includes spreading a coating liquid formed with blending an acrylic resin, a fluothane-grafted acrylic resin, and a siloxane-grafted acrylic resin, or the liquid can be formed with an acrylic resin containing a fluorine compound or a silicon compound, so as to form a self-assembling optical film structure on a coated film surface, thus significantly reducing the cost. As a result, random and irregular array is generated during spreading the coating liquid, so we can effectively reduce the generation of optical interference due to the regular structure, and the product thereby has better brightness enhancement property and can be composed of relatively less layers of optical films. | 08-13-2009 |
Chu Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100237509 | IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING - An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving. | 09-23-2010 |
Chun-Lung Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090328142 | Systems and Methods for Webpage Verification Using Data-Hiding Technology - A system for webpage verification comprises an authentication module configured to authenticate a user identifier if the user identifier is unique in the system, the user identifier being related to the identity of a user, a data-hiding module configured to generate a first data-hidden object based on a unique user identifier, at least one webpage identifier and a base object in accordance with a data-hiding algorithm, each of the at least one webpage identifiers being related to the identity of one of at least one webpage of the user, a memory module to store at least one of the said user identifier, the at least one webpage identifier, the base object, and the required parameters of data-hiding algorithm, and a verification module configured to retrieve the first data-hidden object from one of the at least one webpage based on one of the at least one webpage identifier, retrieve a user identifier and all of the webpage identifiers from the memory module based on the one webpage identifier, generate a second data-hidden object based on the retrieved webpage identifiers, the retrieved user identifier and the base object, and compare the first data-hidden object with the second data-hidden object. | 12-31-2009 |
Chun-Yen Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090195221 | Capacitor charger with a modulated current varying with an input voltage and method thereof - In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery. | 08-06-2009 |
Eric Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090001462 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 01-01-2009 |
| 20110163376 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type. | 07-07-2011 |
| 20120003803 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 01-05-2012 |
Hsin-Chiang Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090284445 | LED DATA INPUT SCHEME WITH SEQUENTIAL SCAN METHOD AND CASCADE CONNECTION FOR LIGHT EMITTING DIODE (LED) DISPLAY SYSTEM - This invention is an architecture of Driver IC used by the LED light systems. Each Driver IC comprises at least one Drive Cell that connects to an individual LED. The LED data are transmitted via a sequential scanning method from Drive Cell to Drive Cell, and from Driver IC to Driver IC that are connected in a cascade manner. | 11-19-2009 |
Huan-Tsung Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100065925 | LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension. | 03-18-2010 |
| 20100078733 | TRANSISTOR PERFORMANCE IMPROVING METHOD WITH METAL GATE - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode. | 04-01-2010 |
| 20120003804 | Local Charge and Work Function Engineering on MOSFET - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension. | 01-05-2012 |
Jia-Chi Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090167993 | METHOD FOR FORMING OPTICAL COMPENSATING FILMS, OPTICAL COMPENSATING FILMS FORMED THEREBY, STRUCTURE OF OPTICAL COMPENSATING FILMS, AND POLARIZING PLATES - The invention provides a method for forming optical compensating films, including: (a) providing a suspension containing clay; (b) adding a mono-functional acrylic oligomer of formula (I) in the suspension, wherein n | 07-02-2009 |
| 20090279176 | ANTIGLARE FILM AND MANUFACTURING METHOD THEREOF - The invention provides an antiglare film. A resin layer is disposed on a substrate. Micro-aggregates are distributed in an interior and over a surface of the resin layer. Each of the micro aggregates has a size of 0.1-3 μm and is formed by aggregating aggregated nano-particles. The micro-aggregates distributing over the surface result in a surface roughness of the resin layer. The weight ratio of the resin layer to the micro-aggregates is 1:0.1-0.7. | 11-12-2009 |
Kuo Bin Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110086504 | METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed. | 04-14-2011 |
| 20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
| 20120086075 | DEVICE WITH ALUMINUM SURFACE PROTECTION - A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer. | 04-12-2012 |
Ming Chuan Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100153636 | CONTROL SYSTEM AND METHOD FOR MEMORY ACCESS - A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data. | 06-17-2010 |
Ming-Feng Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100066465 | DOWN CONVERSION FILTER - A down conversion filter with a plurality of sampling capacitor, wherein at least one sampling capacitor is discharged in sampling phases or charge-summing phases of the other sampling capacitors. | 03-18-2010 |
| 20100130146 | DOWN CONVERSION FILTER AND COMMUNICATION RECEIVING APPARATUS - A down-conversion filter is provided, using first and second input terminals to receive signals that are differentially outputted by a preceding circuit, and using an output terminal to output a down-converted and filtered signal. An output capacitor is coupled to the output terminal. A first switched-capacitor network is arranged between the first input terminal and the output terminal. A second switched-capacitor network is arranged between the second input terminal and the output terminal. Each switched-capacitor network has capacitors, charging switches and charge-summing switches. The charging switches are designed to alternatively couple the capacitors to the first (or second) input terminal. The charge-summing switches are designed to couple the capacitors to the output terminal. | 05-27-2010 |
| 20110248768 | CHARGE DOMAIN FILTER WITH CONTROLLABLE TRANSFER FUNCTIONS AND TRANSFER FUNCTION CONTROL METHODS THEREOF - A charge domain filter with controllable transfer function is disclosed. The charge domain filter has a plurality of switched-capacitor networks, a switching device and a current adder. The switched-capacitor networks are interleaving controlled, and each have an input terminal and an output terminal, and the input terminals of all of the switched-capacitor networks are connected together to be coupled to an input signal. The switching device is designed for transfer function control, and is operated according to a switch control signal. The switching device determines connections between the output terminals of the switched-capacitor networks and how the output terminals of the switched-capacitor networks are coupled to the current adder and thereby generates at least one current adder input. The at least one current adder input is received by the current adder, and the current adder outputs an output signal accordingly. | 10-13-2011 |
Pei-Cheng Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090080676 | Driver circuit and driving method for electrostatic loudspeaker - The present invention discloses a driver circuit for an electrostatic loudspeaker, comprising: a digital modulation encoder for receiving a digital audio signal and a fixed frequency pulse signal, and mixing them by modulation; a digital to analog converter for converting the output of the digital modulation encoder to an analog signal; a transformer for adjusting the voltage amplitude of the analog signal; and a demodulator for demodulating the adjusted analog signal to driver a speaker. | 03-26-2009 |
| 20100066266 | Led bulb, light emitting device control method, and light emitting device controller circuit with dimming function adjustable by AC signal - The present invention discloses a light emitting device control method for adjusting the brightness of the light emitting device by an AC signal, comprising: receiving a signal having a turn ON angle and converting the signal to a DC signal; obtaining an average of the DC signal level, the average being a function of the turn ON angle; determining a reference voltage of a current source circuit according to the average of the DC signal level; and controlling a current flow through the light emitting device by the current source circuit. | 03-18-2010 |
Sheng-Yung Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110296076 | HYBRID DATA TRANSMISSION EXCHANGER AND HYBRID DATA TRANSMISSION METHOD - The present invention discloses a hybrid data transmission exchanger and a hybrid data transmission method, whereby hosts can access storage units and share data. The hybrid data transmission exchanger comprises an embedded central processing unit, a virtual bridge/switch unit, an optical fiber network connection unit and an Ethernet connection unit. The embedded central processing unit is connected with the storage units and detects the virtual bridge/switch unit, optical fiber network connection unit and Ethernet connection unit to detect the connection states of a host. A host can directly access the storage units via the optical fiber network connection unit or the Ethernet connection unit. When a host is linked to the exchanger via a PCIe interface, the virtual bridge/switch unit converts an address area and a request identification code of the host to correspond to the embedded central processing unit, whereby the host can access storage units. | 12-01-2011 |
Ting-Li Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080313601 | Speech IC Simulation Method, System and Medium thereof - In a speech IC simulation method, a system, a medium and a firmware code generation method, the speech IC simulation method for obtaining a simulation result of a speech IC project includes the steps of establishing and compiling a speech IC project in a wizard interface, setting and displaying a visualized in-circuit emulator (ICE) allocation interactively corresponding to the speech IC project in a visualized allocation interface, and setting and performing the clips and corresponsive system trigger events in a visualized clip editing and event setting interface if a modification of the speech IC project is required. Moreover, the firmware code from compiling the speech IC project may be outputted through an output port such as an USB port or a printer port or recorded in a memory of a circuit emulator. | 12-18-2008 |
Tong-Yuh Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100243442 | ELECTROCHEMICAL SENSING TEST PIECE WITHOUT HEMOCYTE INTERFERENCE - The present invention provides an electrochemical sensing test piece without hemocyte interference, including a main body, electrode unit, reaction tank and chemical reaction zone. The detection zone of the electrode unit corresponds to the inserting end of the main body, and the reaction zone of the electrode unit corresponds to the sensing end of the main body. The reaction tank is arranged onto the sensing end correspondingly to the reaction zone of the electrode unit. The reaction tank is provided with a porous filter layer, whose aperture must be less than 6 μm for or separation of hemocyte in the blood sample. A chemical reaction zone is arranged between the porous filter layer and the reaction zone of the electrode unit. The hemocyte of the blood sample can be blocked and filtered by the porous filter layer, ensuring that the serum of blood sample can enter into the chemical reaction zone. | 09-30-2010 |
Tsung-Cheng Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080299769 | SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS - A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film. | 12-04-2008 |
| 20100273286 | Method Of Fabricating An Integrated CMOS-MEMS Device - An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure. | 10-28-2010 |
Yin Chin Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120020164 | TEST METHOD FOR SCREENING MANUFACTURING DEFECTS IN A MEMORY ARRAY - A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell at an intersection of the program conductive line and a conductive line extending in a second direction to a selected high value, and determining whether a cell initially at a low value and associated with a conductive line extending in the first direction and adjacent to the program conductive line is disturbed. | 01-26-2012 |
Yu-Lien Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 12-18-2008 |
| 20110006390 | STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME - A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench. | 01-13-2011 |
| 20110269287 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin. | 11-03-2011 |
| 20120018848 | HIGH SURFACE DOPANT CONCENTRATION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer. | 01-26-2012 |
| 20120070953 | METHOD OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical. | 03-22-2012 |
| 20120112248 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures. | 05-10-2012 |
Yung-Chi Huang, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100328947 | LIGHT-EMITTING DIODE LIGHT SOURCE ASSEMBLY WITH HEAT DISSIPATION BASE - A light-emitting diode (LED) light source assembly with a heat dissipation base is provided. The LED light source assembly includes the heat dissipation base and a light bar. The light bar includes a flexible printed circuit (FPC) board and at least one LED unit which is disposed on the FPC board and electrically connected to the FPC board. The heat dissipation base has two retaining recesses for lodging the side portions of the FPC board, so the FPC board can be thermally conductively connected to the heat dissipation base. Because of the flexibility of the FPC board, it is easy to lodge the FPC board in the heat dissipation base via the retaining recesses. Thus, the cost for arranging the light bar can be economized. | 12-30-2010 |