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Huang, Hsin-Chu
Bob Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100006398 | SEGREGATING APPARATUS - An apparatus for segregating electronic components that engages and stops each of a plurality of electronic packages passing down a singulation tube is disclosed. In addition, the segregating apparatus is cable of segregating the electronic packages even though some of them had been linked together during the sealing process. The segregating apparatus includes a first swing arm to clip a electronic component, a second swing arm to clip another electronic component, and a third swing arm to depart the two electronic components, where all of components of the segregating apparatus are driven by a single driving force, reducing the size of the apparatus and the time needed for the segregating process. | 01-14-2010 |
Chang-Yu Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110141086 | ELECTROPHORETIC DISPLAY AND METHOD OF DRIVING THE SAME - An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage. | 06-16-2011 |
Chao Chien Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110032230 | CONTROL DEVICE AND CONTROL METHOD FOR IMAGE DISPLAY - A control device for an image display includes at least two reference points, a modulation unit and a remote controller. The modulation unit modulates the light of a predetermined spectrum generated by the reference points with a brightness variation cycle. The modulation unit controls the reference points to emit the light with a first brightness within a first period of the brightness variation cycle and to emit the light with a second brightness within a second period of the brightness variation cycle, wherein the first brightness and the second brightness are not zero gray level. The remote controller captures the light of the predetermined spectrum with a sampling cycle and demodulates an image variation of the reference points with respect to the remote controller. The present invention further provides a control method for an image display. | 02-10-2011 |
Chau-Shiang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100136868 | METHOD OF FORMING A COLOR FILTER TOUCH SENSING SUBSTRATE - A method of forming a color filter touch sensing substrate integrates touch-sensing structures/elements of a touch panel into the inner side of the color filter substrate, which faces a thin film transistor substrate, and forms patterned assistant electrodes on the surfaces of the transparent sensing pads for decreasing the equivalent resistance of the touch-sensing structures/elements. Moreover, since an adjacent transparent conductive layer and an assistant electrode layer are patterned to form the transparent sensing pads and the patterned assistant electrodes, a simplified pattern-transferring process can be applied to the transparent sensing pads and the patterned assistant electrodes, or bridge structures can be formed from the assistant electrode layer for electrically connecting between some transparent sensing pads. Therefore, the forming process is simplified. | 06-03-2010 |
| 20110157084 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of diode ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each diode ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
Cheng-Lin Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090209098 | Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage - A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber. | 08-20-2009 |
| 20090209106 | In Situ Cu Seed Layer Formation for Improving Sidewall Coverage - A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer. | 08-20-2009 |
| 20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
| 20100171220 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 07-08-2010 |
| 20110171826 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 07-14-2011 |
Chia-Horng Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110080396 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 04-07-2011 |
| 20110115780 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 05-19-2011 |
Chia-Te Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100263945 | Rechargeable Electromagnetic Pen - A rechargeable electromagnetic pen is disclosed. The rechargeable electromagnetic pen comprises a rechargeable and storable electrical power source system, an electrical power receiving terminal and a signal transformation circuit. The electrical power source system provides the rechargeable electromagnetic pen with electrical power for emitting electromagnetic signal to an array of antenna loops of a digital tablet. The electrical power-receiving terminal receives electrical power signal generating from electric energy transformation and transmission between the electrical power receiving terminal and a charge site. The signal transformation circuit processes and transforms the electrical power signal and charges the electrical power source system. | 10-21-2010 |
Chien-Chao Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090203202 | Strained Gate Electrodes in Semiconductor Devices - Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode. | 08-13-2009 |
Chien-Cheng Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100171915 | Liquid Crystal Display Device - An LCD device having a backlight module, a display module and an adhesive layer is provided. The backlight module has an inner fringe for holding the display module. The display module sequentially includes a lower polarizer, a display panel and an upper polarizer. The edge of the upper surface of the display panel is exposed because the area of the upper polarizer is smaller than the area of the display panel. The adhesive layer has a first adhesive film and a second adhesive film. The display module is disposed on the inner fringe of the backlight module by using the adhesive layer wherein the first adhesive film is on the side wall of the backlight module and portion of the edge of the upper surface of the display panel, the second adhesive film is on the portion of the first adhesive film and the exposed edge of upper surface of the display panel. | 07-08-2010 |
Chien-Hsing Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090013117 | SYSTEM AND METHOD FOR GENERATING INTERRUPT - A system and a method for generating an interrupt are provided. In the interrupt generating method, a time-out mechanism is executed by a second network component of a computer system after a packet processing action is finished. An interrupt is generated by the second network component only if a first network component of the computer system does not execute a polling action during a predefined period after the time-out mechanism is processed. Thus, it is not necessary to generate the interrupt every time after processing a network packet, so that less interrupts are generated and accordingly the loading of the computer system is reduced. Moreover, the reaction time of the computer system is kept to ensure the efficiency of the computer system. | 01-08-2009 |
Chien-Jung Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110096298 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and do not cross each other. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged in a row. The first dichroic film reflects the first light beam and transmitting the second light beam, the second dichroic film reflects the second light beam, the first dichroic film and the second dichroic film transmit the third light beam, and the third dichroic film reflects the third light beam. | 04-28-2011 |
| 20110096299 | ILLUMINATION SYSTEM AND PROJECTION APPARATUS HAVING THE SAME - An illumination system includes a chip package, a first dichroic film, a second dichroic film, and a third dichroic film. The first dichroic film, the second dichroic film, and the third dichroic film are not parallel to each other and cross one another at an identical region. The chip package includes a first light-emitting chip capable of emitting a first light beam, a second light-emitting chip capable of emitting a second light beam, and a third light-emitting chip capable of emitting a third light beam. The first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are arranged to form a delta arrangement. The first dichroic film is capable of reflecting the first light beam, and the second dichroic film is capable of reflecting the second light beam. The first dichroic film is capable of transmitting the third light beam, and the third dichroic film is capable of reflecting the third light beam. | 04-28-2011 |
Chi-Heng Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090172617 | Advisory System for Verifying Sensitive Circuits in Chip-Design - A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits. | 07-02-2009 |
Chi-Hsiang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110155460 | SUBSTRATE AND SUBSTRATE BONDING DEVICE USING THE SAME - A substrate and a substrate bonding device using the same are provided. The substrate includes a base, upper and lower metal layers, and upper and lower covering layers. The base has an upper surface, a lower surface and a through-hole passing there through, wherein the upper and lower covering layers respectively covers the upper and lower metal layers respectively disposed on the upper and lower surfaces of the base. The lower metal layer has an electrical bonding portion and a strengthening bonding portion insulated with each other. The strengthening bonding portion enhances the bonding strength between the substrate and another substrate. The upper metal layer is electrically connected to the electrical bonding portion via the through hole. The lower covering layer exposes the electrical bonding portion and the strengthening bonding portion so as to be respectively connected with two bonding portions of the another substrate. | 06-30-2011 |
Chi-Hsun Huang, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090033883 | PROJECTION APPARATUS AND METHOD FOR ACTIVATING A PROJECTION APPARATUS - A projection apparatus includes an illuminating unit, an imaging unit, a lens unit, and a control unit. The illuminating unit includes a light source, and a light source driving module operable to drive the light source to provide an illumination beam. The imaging unit is operable so as to modulate the illumination beam into an image beam. The lens unit is disposed on an optical path of the image beam for projecting the image beam. The control unit is coupled electrically to the illuminating unit and the imaging unit. The control unit is configured to execute an activating thread for initializing the imaging unit after controlling initial driving of the light source by the light source driving module, and a monitoring thread for monitoring the light source driving module for a success signal that indicates successful provision of the illumination beam by the light source. | 02-05-2009 |
Ching-Cheng Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080284016 | Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad. | 11-20-2008 |
Ching-Chou Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110199789 | LIGHT SOURCE APPARATUS - A light source apparatus including a light source, an optical fiber, a light guide module, and a light shape adjustment element is provided. The light source emits a light beam. The optical fiber disposed in a transmission path of the light beam has a light incident end and a light emitting end. The light beam enters the optical fiber through the light incident end and leaves the optical fiber through the light emitting end. The light guide module has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface and the second surface. The light beam from the light emitting end enters the light guide module through the light incident surface. The light shape adjustment element is connected to the light guide module and capable of changing a light shape of an emitted light from the light guide module. | 08-18-2011 |
Ching-Yu Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080308894 | Electro-Optical Apparatus and a Circuit Bonding Detection Device and Detection Method Thereof - This invention provides a circuit bonding detection device, a detection method thereof and an electro-optical apparatus incorporating the circuit bonding detection device. The circuit bonding detection device includes a substrate, a circuit module, a set of sensors, and a detection unit. A plurality of contact pads is disposed on the substrate. The circuit module includes a plurality of conductive bumps corresponding to the contact pads. The sensors are disposed on two sides of at least one of contact pads or of the corresponding conductive bumps. The detection unit is electrically coupled with the set of sensors and transmits a fault signal when at least one of the contact pads and the corresponding conductive bumps deforms and contacts the sensors. | 12-18-2008 |
Chin-Yi Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090159946 | Logic Non-Volatile Memory Cell with Improved Data Retention Ability - A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors. | 06-25-2009 |
Chun-Kai Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090195562 | Display Device and Driving Method Thereof - A driving method for driving a display device is provided. The driving device includes at least a pixel. The pixel has a first, a second, and a third sub-pixels respectively associated with three primary colors. The driving method includes the steps of driving the first, second and third sub-pixels respectively in accordance with a first, a second and a third driving sequences during a first, a second and a third frame periods. Moreover, the first, the second and the third driving sequences are different from each other. A display device applying said driving method is also provided herein. | 08-06-2009 |
| 20090256833 | Method for Driving Display Device - A method for driving a display device is provided herein. The display device includes a plurality of scan lines. The method comprises following steps: dividing the scan lines into a plurality of groups, each of which comprises at least two scan lines, i.e. a first and a second scan line; during a first frame period, sequentially enabling the first and second scan line of each group in accordance with a first driving sequence; and during a second frame period, sequentially enabling the first and second scan line of each group in accordance with a second driving sequence, wherein the first driving sequence is different with the second driving sequence. | 10-15-2009 |
Hong-Ji Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100182558 | LIQUID CRYSTAL DISPLAY PANEL - According to the present invention, an LCD panel includes a first substrate, a second substrate placed opposite to the first substrate, and a liquid crystal layer placed between the first substrate and the second substrate. The first substrate includes a pixel electrode and a first common electrode. The pixel electrode includes a plurality of first protruding nodes, and the first common electrode includes a plurality of second protruding nodes interleaved with the plurality of first protruding nodes. The second substrate includes a second common electrode corresponding to the first common electrode. The second common electrode includes a plurality of third protruding nodes corresponding to the second protruding nodes. | 07-22-2010 |
| 20100220068 | Method for Mitigating Pooling Mura on Liquid Crystal Display Apparatus and Liquid Crystal Display Apparatus - A method for mitigating pooling mura on LCD apparatus and a LCD apparatus are provided. The method is adapted for a LCD apparatus having a plurality of pixels. The LCD apparatus is for displaying frames according to a received original display data, and each of at least a part of the pixels comprises two pixel electrodes to drive a plurality of liquid crystal molecules between the two pixel electrodes. The method comprises changing a corresponding portion of the original display data so as to rotate at least a part of the liquid crystal molecules between the two pixel electrodes of the pressed pixel toward a natural angle; and maintaining another corresponding portion of the original display data. The natural angle is a finally-presented tilt angle of the liquid crystal molecules between the corresponding two pixel electrodes having substantially no potential difference therebetween. | 09-02-2010 |
| 20110057898 | TOUCH-SENSING STRUCTURE FOR TOUCH PANEL AND TOUCH-SENSING METHOD THEREOF - In a touch-sensing structure for a touch panel and a touch-sensing method thereof, the touch-sensing structure includes a plurality of first conducting wires paralleled to each other and a first conductor. A terminal of each first conducting wire is electrically coupled to the first conductor, so as to divide the conductor into a plurality of first line segments. The resistance of each first conducting wire is smaller than that of each first line segment. Wherein, when the displaying area of the touch panel receives an external force, a first conducting wire corresponding to the position designated by the external force is electrically coupled to a reference potential. | 03-10-2011 |
Hon-Lin Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100090319 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 04-15-2010 |
| 20100102453 | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure - A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV. | 04-29-2010 |
| 20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 11-04-2010 |
| 20100330798 | Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 | 12-30-2010 |
| 20110049706 | Front Side Copper Post Joint Structure for Temporary Bond in TSV Application - An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via. | 03-03-2011 |
| 20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 07-07-2011 |
Hsin-Chang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100238386 | Display panel and method of repairing bright point thereof - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point | 09-23-2010 |
Hsuen-Ying Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090174831 | LIQUID CRYSTAL DISPLAY WITH UNIFORM FEED-THROUGH VOLTAGE - A liquid crystal display with uniform feed-through voltage includes a plurality of data lines for receiving a plurality of data signals respectively, a plurality of gate lines for receiving a plurality of gate signals respectively, a plurality of common lines for receiving a common voltage, a plurality of storage units, a plurality of first switches, and a plurality of second switches. Each storage unit includes a first liquid crystal capacitor and a second liquid crystal capacitor coupled to a corresponding common line. Each first switch is coupled to a corresponding data line, a corresponding gate line, and a corresponding first liquid crystal capacitor. Each second switch is coupled to a corresponding gate line, a corresponding first switch, and a corresponding second liquid crystal capacitor. The capacitance of the gate-source capacitor of each first switch is greater than the capacitance of the gate-source capacitor of each second switch. | 07-09-2009 |
Hua-Chiang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090051334 | Droop circuits and multi-phase DC-DC converters - A droop circuit of a DC-DC converter is provided, wherein the DC-DC converter includes an output inductor coupled between an output of the DC-DC converter and a phase node for providing an output voltage. A current sense device is coupled between the phase node and the output of the DC-DC converter, includes an inductor coupled to the phase node and senses a current from the phase node. A first resistor is coupled to the current sense device. An amplifier circuit includes an amplifier having an inverting input, a non-inverting input coupled to the first resistor and an output directly connected to the inverting input, and a second resistor coupled between the inverting input and the output of the DC-DC converter. The amplifier circuit provides a droop current according to the second resistor and a voltage difference between the non-inverting input and the output of the DC-DC converter, and the voltage difference is related to the current. | 02-26-2009 |
| 20090051335 | Multi-phase DC-DC converter and method for balancing channel currents - A multi-phase DC-DC converter is provided. A plurality of switching sets are coupled to an output, wherein each switching set includes a phase node. A plurality of inductors are separately coupled between the phase nodes and the output. A sense circuit has a plurality of sense units separately coupled to the phase nodes, each sensing a signal from the corresponding phase node and generating a sensing signal. A PWM generator includes a plurality of subtracting units, each subtracting a first signal from one of the sensing signals to generate a difference signal, wherein the first signal is generated by summing each of the sensing signals divided by a predetermined value except for the one of the sensing signals. The PWM generator generates a plurality of PWM signals to balance the currents of the inductors according to the difference signals. | 02-26-2009 |
| 20090153110 | Control method for multi-phase DC-DC controller and multi-phase DC-DC controller - A multi-phase DC-DC controller. The multi-phase DC-DC controller comprises converter channels, a channel control device and a power control device. Each converter channel comprises a switch device, a first output node and an inductor coupled between the switch device and the first output node. The channel control device generates adjusted pulse width modulation signals according to control signals of the converter channels to respectively control operation of the switch device in each converter channel. The power control device generates the control signals according to sensed currents in the converter channels so as to dynamically turn on or off each converter channel according to the sensed currents. | 06-18-2009 |
| 20090153114 | DC-DC converters with transient response control - A DC-DC converter used to convert an input voltage to an output voltage is disclosed. The DC-DC converter comprises a pulse-width-modulation (PWM) generator, a transient boost circuit, a logic circuit, a switching device, and a buck circuit. The pulse-width-modulation (PWM) generator generates a PWM signal according to the output voltage. The transient boost circuit generates an adjusting signal according to the variation of the output voltage. The logic circuit generates a switch signal according to the PWM signal and the adjusting signal. The switching signal is at a high level when the PWM signal or the adjusting signal is at the high level, and the switching signal is at a low level when the PWM signal and the adjusting signal are at the low level. The switching device converts the input voltage to a driving signal according to the switching signal. The buck circuit receives the driving signal to generate the output voltage. | 06-18-2009 |
Huan-Tsung Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
| 20080258185 | Semiconductor structure with dielectric-sealed doped region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 10-23-2008 |
Hung-Sheng Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110096567 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate is adapted for a backlight module having at least one light emitting device, and the light guide plate includes a light emitting surface, a surface opposite to the light emitting surface, a light incident surface connected with the light emitting surface and the surface, and a plurality of microstructures disposed on the light emitting surface or the surface. 90 percent or more of the surface or the light emitting surface is flat. At least one of the light emitting devices is disposed beside the light incident surface and capable of emitting a light beam. The light incident surface is capable of making the light beam enter the light guide plate and the light emitting surface is capable of making the light beam transmit outside the light guide plate. A backlight module is also provided. | 04-28-2011 |
Jia-Bin Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100289432 | Light emitting apparatus and control method thereof - A light emitting apparatus and a control method thereof are provided. The light emitting apparatus has a semiconductor device capable of emitting light, and the control method includes the following descriptions. A driving power of the semiconductor device is reduced to an ideal power stepwise and gradually. After every time the driving power of the semiconductor device is reduced, the semiconductor device continually emits the light by the reduced driving power within a predetermined time. | 11-18-2010 |
Ji-Chung Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100088129 | Technology Selection and Pricing System - A method of selecting a technology for manufacturing an integrated circuit includes designating candidate technologies for manufacturing the integrated circuit; generating design and performance data from the integrated circuit, wherein the design and performance data are generated for each of the candidate technologies; and generating die prices from the integrated circuit, wherein the die prices are generated for each of the candidate technologies. | 04-08-2010 |
Jiun-Kai Huang, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110001504 | METHOD AND APPARATUS OF DEEMBEDDING - Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures. | 01-06-2011 |
Jung-Yen Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100171905 | TRANSFLECTIVE DISPLAY PANEL - A transflective display panel includes a first substrate, a plurality of electroluminescent (EL) elements disposed on the first substrate, a plurality of reflectors disposed on the first substrate, a second substrate disposed opposite to the first substrate, a plurality of transparent electrodes disposed on a side of the second substrate opposite to the first substrate, a plurality of color filter layers disposed on a side of the second substrate opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. Accordingly, a problem of insufficient contrast ratio of the transflective display panel can be solved, when the ambient light is too high. | 07-08-2010 |
| 20110037729 | OLED TOUCH PANEL AND METHOD OF FORMING THE SAME - A displaying region and a sensing region are defined in each pixel region of the OLED touch panel of the present invention. The readout thin film transistor of the sensing region is formed by the same processes with the drive thin film transistor of the displaying region. The top and bottom electrodes of the optical sensor are formed by the same processes with the top and bottom electrodes of the OLED. Accordingly, the present invention can just add a step of forming the patterned sensing dielectric layer to the processes of forming an OLED panel to integrate the optical sensor into the pixel region of the OLED panel. Thus, an OLED touch panel is formed. | 02-17-2011 |
Ke Ming Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100247742 | Three-dimensional object forming apparatus and method for forming three-dimensional object - A three-dimensional object forming apparatus is provided, which at least comprises: a construction stage, a printing module, plural temporary storage tanks, plural powder supplying tanks, a construction tank, a printing quality inspection component for forming a pattern to determine whether the printing module is blocked or not, a maintenance device, and a dust-proof device. | 09-30-2010 |
K. T. Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110001194 | Hybrid Process for Forming Metal Gates - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon. | 01-06-2011 |
Kuan-Chieh Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090263674 | Forming Sensing Elements above a Semiconductor Substrate - An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers. | 10-22-2009 |
Kuan-Chun Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110141420 | MULTI-DOMAIN VERTICAL ALIGNMENT LIQUID CRYSTAL DISPLAY DEVICE AND PIXEL STRUCTURE THEREOF - An MVA LCD device includes a first alignment region, a second alignment region, a third alignment region, and a fourth alignment region. The liquid crystal molecules disposed in the first alignment region have a first aligning direction, and the azimuth angle of the first aligning direction is substantially between 70 and 110 degrees. The liquid crystal molecules disposed in the second alignment region have a second aligning direction, and the azimuth angle of the second aligning direction is substantially between 160 and 200 degrees. The liquid crystal molecules disposed in the third alignment region have a third aligning direction, and the azimuth angle of the third aligning direction is substantially between 250 and 290 degrees. The liquid crystal molecules disposed in the fourth alignment region have a fourth aligning direction, and the azimuth angle of the fourth aligning direction is substantially between −20 and 20 degrees. | 06-16-2011 |
Kun-Fu Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100096630 | Bottom-Gate Thin Film Transistor and Method of Fabricating the Same - A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 10 | 04-22-2010 |
| 20110012114 | Bottom-Gate Thin Film Transistor and Method of Fabricating the Same - A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 10 | 01-20-2011 |
Kung-Chieh Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110057898 | TOUCH-SENSING STRUCTURE FOR TOUCH PANEL AND TOUCH-SENSING METHOD THEREOF - In a touch-sensing structure for a touch panel and a touch-sensing method thereof, the touch-sensing structure includes a plurality of first conducting wires paralleled to each other and a first conductor. A terminal of each first conducting wire is electrically coupled to the first conductor, so as to divide the conductor into a plurality of first line segments. The resistance of each first conducting wire is smaller than that of each first line segment. Wherein, when the displaying area of the touch panel receives an external force, a first conducting wire corresponding to the position designated by the external force is electrically coupled to a reference potential. | 03-10-2011 |
| 20110157061 | Touch-Sensing Display Device and Touch-Sensing Module Thereof - A touch-sensing display device, specifically to a borderless touch-sensing display device, is disclosed. The touch-sensing display device includes a display module and a touch-sensing module. The touch-sensing module includes a first sensing sheet and a second sensing sheet, wherein a space exists between the first sensing sheet and the second sensing sheet. The first sensing sheet includes a lens layer, a plurality of first conductive portions, and a conductive film, wherein the conductive film is disposed on the lens layer while the first conductive portions are distributed on two opposite sides of the lens layer. The second sensing sheet includes a substrate, a plurality of second conductive portions, and a plurality of conductive strips, wherein the second conductive portions are selectively distributed on one of two sides of the substrate while the conductive strips are respectively connected to the second conductive portions and have different voltages. | 06-30-2011 |
Kuo-Bin Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
Kuo-Tai Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080303102 | Strained Isolation Regions - An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 12-11-2008 |
| 20090014813 | Metal Gates of PMOS Devices Having High Work Functions - A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device. | 01-15-2009 |
| 20090230479 | Hybrid Process for Forming Metal Gates of MOS Devices - A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer. | 09-17-2009 |
Kuo-Tung Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100149762 | FIXING STRUCTURE AND BACKLIGHT MODULE USING THE SAME - A fixing structure and a backlight module using the same are provided. The fixing structure is used for fixing a circuit board. The circuit board with several openings has an upper surface and a lower surface. The fixing structure includes a back plate and several hooks. The back plate has a contact surface. These hooks are disposed on the contact surface. The hooks go through the openings so that the contact surface contacts the lower surface. The hooks move toward the walls of the openings and press against the upper surface so as to fix the circuit board onto the back plate. | 06-17-2010 |
Mei-Lien Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080309866 | Display Panel with Photo-Curable Sealant and Manufacture Method Thereof - A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure. | 12-18-2008 |
| 20110117804 | Display Panel with Photo-Curable Sealant and Manufacture Method Thereof - A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure. | 05-19-2011 |
Ming-Jie Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110076832 | DUAL ETCH METHOD OF DEFINING ACTIVE AREA IN SEMICONDUCTOR DEVICE - A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature. | 03-31-2011 |
Po-Chin Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090135195 | Liquid Crystal Display and Method for Adjusting Backlight Brightness Thereof - A liquid crystal display includes a scaler module, a field-programmable gate array (FPGA) module, a buffer, a backlight module and a LCD module. The FPGA module includes a regional peak detector, a backlight control unit and a pixel value control unit. The regional peak detector is configured for detecting a maximum pixel value of each image region of each image. The backlight control unit is configured for selectively adjusting the backlight brightness of one or more image regions of each image. The pixel value control unit is configured for adjusting pixel values of the one or more image regions of each image by shifting binary pixel values to compensate for the influence of backlight adjustment. A method for adjusting backlight brightness of a liquid crystal display is also provided. | 05-28-2009 |
| 20090135206 | Color management system with advance function module and color management process for display device - A color management system for display device includes a color management controller, a color sensor, and an advance function module configured to implement a process (a) or a process (b) applied to multiple PWM signals generated from the color management controller. Process (a) includes the steps of using a reset signal generated by and synchronized with an image signal, and a counter with special bit length and counting frequency to generate a reference signal synchronized with the image signal, and using the reference signal to synchronize the PWM signals with the image signal as output. Process (b) includes the steps of using a reset signal with special frequency and a counter with special bit length and counting frequency to generate multiple synchronized reference signals with respective different phases, and generating multiple synchronized PWM signals with respective different phases as output by the use of the reference signals. | 05-28-2009 |
Sen-Huang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100297461 | COLOR FILTER BY COPPER AND SILVER FILM AND METHOD FOR MAKING SAME - The present invention discloses a color filter by copper and silver film, comprising: a lower copper layer; a lower silver layer formed on the lower copper layer; a medium formed on the lower silver layer; an upper copper layer formed on the medium; and an upper silver layer formed on the upper copper layer. | 11-25-2010 |
| 20110049565 | OPTOELECTRONIC DEVICE AND PROCESS FOR MAKING SAME - The present invention discloses an optoelectronic device, comprising: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si1-xGex) or silicon carbide (Si1-yCy), wherein 0| 03-03-2011 | |
Shao-Chang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080211027 | ESD structure without ballasting resistors - An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor. | 09-04-2008 |
Sheng-Wen Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100283402 | BACKLIGHT MODULE FOR LCD DEVICE - A backlight module includes a connector capable of performing voltage conversion or a voltage converter capable of transmitting signals. The connector or the voltage converter, disposed between an inverter and a lamp set, receives low-voltage signals generated by the inverter, performs voltage conversion, and outputs high-voltage signals for driving the lamp set. | 11-11-2010 |
Shen-Yi Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100238386 | Display panel and method of repairing bright point thereof - A display panel has a portion of a color filter or patterned color layer with a thickness of at least half of the cell gap of the display panel, wherein the repair method includes providing a energy light beam to the portion of the color filter or the patterned color layer in the sub-pixel region with a bright point defect to make the portion of the color filter or patterned color layer have porous structure so that bright point is repaired to become a grey point or a dark point | 09-23-2010 |
Shih-Lang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110000305 | Stress Sensor and Assembly Method Thereof - A stress sensor includes a circuit board having a stress sensitive structure, a pointing stick and a metallic back plate. The stress sensitive structure includes a stress deformation region and multiple resistors located on the stress deformation region. The pointing stick is disposed on a top of the circuit board and connected to the stress sensitive structure. The metallic back plate includes at least one fixing material coating region, and thus the fixing edges of the circuit board are fixed on the corresponding fixing material coating region. An assembly method for the stress sensor is also provided. | 01-06-2011 |
Shih-Shiung Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080310761 | Image Process Method and Apparatus for Image Enlargement and Enhancement - An image processing device includes an image acquisition module, a memory module, and an image signal processing module, for performing an image enlargement and enhancement. The image acquisition module sequentially reads in an image block, including a unit pixel matrix and an exterior pixel matrix, wherein each pixel matrix includes a plurality of pixels and each pixel is associated with a parameter. The memory module stores a plurality of predefined edge patterns. The image signal processing module compares a loaded image block with predefined edge patterns, and determines if it is an edge block. Then, the image signal processing module further classifies its pixels into two groups, and calculates a continuous separating boundary between the two groups. Finally, the image signal processing module enlarges an edge block by placing new pixels inside its unit pixel matrix, wherein the new pixel parameters are extrapolated from the two classified pixel groups to maintain a sharp edge boundary. For those that are not edge blocks, interpolations are performed by the image signal processing module to derive smooth enlargements. | 12-18-2008 |
Shu-Hui Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080230798 | ACTIVE MATRIX ORGANIC ELECTROLUMINESCENT SUBSTRATE AND METHOD OF MAKING THE SAME - An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region. | 09-25-2008 |
| 20110148780 | TOUCH PANEL AND FABRICATING METHOD THEREOF - A method of fabricating touch panel includes the following steps. A base is provided. A first transparent conductive layer is formed on the base. A first screen printing process is performed to form a first patterned sacrificial layer on the first transparent conductive layer, and the first patterned sacrificial layer is used to pattern the first transparent conductive layer to form a patterned sensing pad layer. A second screen printing process is carried out to form a patterned insulating layer. A second transparent conductive layer is formed on the base. A third screen printing process is performed to form a second patterned sacrificial layer, and the second patterned sacrificial layer is used to pattern the second transparent conductive layer to form a patterned bridge line layer. | 06-23-2011 |
Shun-Tien Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090237385 | Display Apparatus and Power Control Circuit thereof - In a display apparatus and a power control circuit thereof, the power control circuit includes an image signal input terminal, a resistor-capacitor (RC) filter and a switch. The image signal input terminal is configured for receiving an image signal and providing a waiting-for-processing signal corresponding to the image signal. The RC filter is configured for receiving the waiting-for-processing signal and filtering out an alternating-current (AC) component of the waiting-for-processing signal to generate a switch control signal. The switch is electrically connected between a power supply and an electronic element, and configured for receiving the switch control signal and making the switch control signal control on-off state of the switch. | 09-24-2009 |
Soon Kang Huang, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080293339 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 11-27-2008 |
| 20100112912 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 05-06-2010 |
| 20100187444 | FIELD-BY-FIELD LASER ANNEALING AND FEED FORWARD PROCESS CONTROL - A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area. | 07-29-2010 |
| 20100277850 | Multi-Zone Electrostatic Chuck and Chucking Method - A method for processing a semiconductor wafer comprises measuring data indicating an amount of warpage of the wafer. At least two different voltages are determined, based on the amount of warpage. The voltages are to be applied to respective portions of the wafer by an electrostatic chuck that is to hold the wafer. The at least two different voltages are applied to hold the respective portions of the wafer while performing a fabrication process on the wafer. | 11-04-2010 |
| 20100291840 | SYSTEM AND METHOD FOR CONDITIONING CHEMICAL MECHANICAL POLISHING APPARATUS USING MULTIPLE CONDITIONING DISKS - A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad. | 11-18-2010 |
Tai-Chun Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080290420 | SiGe or SiC layer on STI sidewalls - A semiconductor structure includes a semiconductor substrate; an opening in the semiconductor substrate; a semiconductor layer in the opening and covering a bottom and sidewalls of the opening, wherein the semiconductor layer and the semiconductor substrate comprise different materials; and a dielectric material over the semiconductor layer and filling a remaining portion of the opening. | 11-27-2008 |
| 20090061586 | Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped. | 03-05-2009 |
| 20100151648 | Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped. | 06-17-2010 |
Ta-Jen Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100123851 | Backlight Module and Display Device Using the Same - The present disclosure is a backlight module including a light guide plate, a supporter, and a light source module. The light guide plate has a light incident side. The supporter has a bottom plate, a sidewall, and a top plate corresponding to the bottom plate. The bottom plate extends from a first end of the sidewall toward the light guide plate, and the top plate extends along a second end of the sidewall toward the light guide plate. The length of the sidewall is longer than the length of the top plate, such that the top plate corresponding to the sidewall forms at least one breach to expose the second end of the sidewall. The bottom plate, the top plate, and the sidewall together form an accommodating space, and the light incident side of the light guide plate is disposed between the top plate and the bottom plate. The light source module is disposed in the accommodating space and partially exposed through the at least one breach. The light source module has at least one light emitting unit and a printed circuit board. The light emitting unit is disposed on the printed circuit board, such that an emitting surface of the light emitting unit can face the light incident side of the light guide plate. | 05-20-2010 |
Te-Chun Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090289259 | PIXEL STRUCTURE OF DISPLAY PANEL AND METHOD OF MAKING THE SAME - A pixel structure of a display panel is provided. The pixel structure includes a first storage capacitor formed by a pixel electrode and a common electrode pattern, and a second storage capacitor formed by an electrode pattern and the common electrode pattern. Accordingly, the storage capacitance is greatly improved without sacrificing the aperture ratio, or the aperture ratio is improved by reducing the area of the storage capacitor while the storage capacitance is maintained. | 11-26-2009 |
Tien-Chun Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090021665 | Active array substrate for flat panel display - An active array substrate for a flat panel display is disclosed. The active array substrate includes a substrate, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first repair lines, a plurality of second repair lines, a plurality of third repair lines. The substrate has a display area. The first repair lines cross and are electrically separated from the second conductive lines. The second repair lines cross and are electrically separated from the second conductive lines. Each of the third repair lines is in electrical connection respectively with one of the first repair lines and one of the second repair lines. The second conductive lines are divided into a plurality of second conductive line groups and each of the second conductive line groups respectively corresponds to one of the third repair lines. | 01-22-2009 |
Tzu-Tse Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090196040 | Light source module of projector - A light source module adapted to a projecting device including a light bulb, a fan, and an air tunnel structure is provided. The fan is located by the light bulb for cooling the light bulb. The air tunnel structure is located respective to the location of the light bulb, for removing the heat generated by the light bulb. The air tunnel structure has a curved inner wall, a plurality of fins, and a tank. The curved inner wall is located inside the air tunnel structure respective to the location of the light bulb. The fins are formed on the curved inner wall for blocking the fragments generated by the explosion of the light bulb. The tank is located by a side of the curved inner wall for carrying the fragments clashing the fins. | 08-06-2009 |
| 20090219492 | DETECTING DEVICE - A detection device is mounted in a projector for detecting relations between an object and the projector. The detection device includes a detecting switch, a connector and a detecting circuit. When the object is placed into the detecting switch, the detecting switch is in an off state. When the object is withdrawn from the detecting switch, the detecting switch is in an on state. The connector is electrically connected to the detecting switch. The detecting circuit is electrically connected to the connector for activating the projector to be operated in a first mode in response to the off state of the detecting switch and activating the projector to be operated in a second mode in response to the on state of the detecting switch. The first mode and the second mode are associated with the temperature inside the projector. | 09-03-2009 |
Wan-Ting Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100315353 | Flexible Touch Display Apparatus - A flexible touch display apparatus includes a flexible substrate, a display unit, a flexible insulation layer and a touch sensor layer. The display unit is disposed on the flexible substrate, the flexible insulation layer is disposed on the display unit, and the touch sensor layer is formed on the flexible insulation layer. The flexible touch display apparatus is light in weight, thin in thickness, flexible and unbreakable. | 12-16-2010 |
Wei-Hao Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090237947 | LAMP POSITION ADJUSTMENT DEVICE AND LAMP MODULE HAVING THE SAME - A lamp position adjustment device includes a bottom frame, a lamp holder, and a lamp mount. The lamp holder is disposed on the bottom frame for supporting the lamp, and the lamp mount is disposed between the lamp holder and the bottom frame. The lamp mount includes a base portion, a first side portion and a second side portion that are respectively connected to two opposite sides of the base portion, a first positioning mechanism, and a second positioning mechanism. The first positioning mechanism is disposed on the base portion to enable the lamp mount to be slidably connected to the bottom frame, and the second positioning mechanism is disposed on the first side portion and the second side portion to enable the lamp mount to be slidably connected to the lamp holder. | 09-24-2009 |
Wei-Kai Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100201903 | FLAT DISPLAY PANEL AND METHOD OF REPAIRING CONDUCTIVE LINES THEREOF - A flat display panel includes a plurality of bridge lines disposed between adjacent common lines. When a short defect occurs, the common line near the short defect can be directly cut off in order to repair the short defect and the common voltage can be transferred through the bridge lines to maintain the normal operation of the flat display panel. | 08-12-2010 |
Wei-Pang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100171905 | TRANSFLECTIVE DISPLAY PANEL - A transflective display panel includes a first substrate, a plurality of electroluminescent (EL) elements disposed on the first substrate, a plurality of reflectors disposed on the first substrate, a second substrate disposed opposite to the first substrate, a plurality of transparent electrodes disposed on a side of the second substrate opposite to the first substrate, a plurality of color filter layers disposed on a side of the second substrate opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. Accordingly, a problem of insufficient contrast ratio of the transflective display panel can be solved, when the ambient light is too high. | 07-08-2010 |
Wen-Chiang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110080383 | Display panel with optimum pad layout of the gate driver - A display panel includes a display area, a first bonding area, and a second bonding area. The second bonding area is used for bonding with a gate driver. The second bonding area includes a plurality of input pads and a plurality of output pads. The plurality of input pads is disposed on the two sides of the second bonding area in the first direction and on the two sides of the second bonding area only the plurality of input pads is disposed in the second direction. The plurality of output pads is disposed on the center region of the second bonding area in the first direction and on the center region of the second bonding area only the plurality of output pads is disposed in the second direction. | 04-07-2011 |
Wen-Ruei Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090213339 | Projector and optical engine thereof - An optical engine includes a light source system for providing an incident light beam, a reflective light valve, a first case, a projection lens and a second case. The reflective light valve is disposed in the first case for receiving the incident light beam, reflecting and outputting an image light beam or a dumped light beam. The first case provides a first opening located in the light path of the dumped light beam. The projection lens is connected to the first case for receiving and projecting the image light beam to form an image. The second case intercommunicates with the first case via the first opening. The dumped light beam enters the second case through the first opening, and is reflected twice or more inside the second case. Moreover, the inner wall of the second case applies to absorb the energy of the dumped light beam. | 08-27-2009 |
Wen-Sheh Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110171795 | FinFET LDD and Source Drain Implant Technique - A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region. | 07-14-2011 |
Yao-Te Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100240215 | Multi-Sacrificial Layer and Method - MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode. | 09-23-2010 |
Yen-Chang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100135003 | Backlight Module and Liquid Crystal Display Module Using the Backlight Module - This present invention discloses a backlight module and a flat display device using the backlight module. The backlight module has a plastic base having a plastic plate and a plastic frame, wherein a light guide plate is disposed on the plastic plate. The plastic plate is light reflective and has a thickness ranging from 0.2 mm to 0.9 mm. The plastic plate is used to reflect light leaking from the light guide plate. The reflectivity of the plastic plate to the visible light with wavelength ranging from 410 nm to 780 nm ranges from 80% to 95%. | 06-03-2010 |
| 20100165658 | Light Guide Plate Having Lateral Optical Structures and Backlight Module Having the Light Guide Plate - The present invention discloses a light guide plate and a backlight module having the same. The light guide plate includes a light emitting surface, a light incident surface, a light reflecting surface, and a plurality of prisms disposed on the light reflecting surface. The disposition direction of the prisms can be parallel or perpendicular to the lengthwise direction of the light reflecting surface. An inclined angle may exist between the disposition direction of the prisms and the lengthwise of the light reflecting surface. The backlight module includes a light guide plate, a light source, and an optical film set, wherein the light source is disposed near the light incident surface. The optical film set partially covers the light emitting surface, wherein a distance exists between a vertex of the prism and an edge of the optical film set. | 07-01-2010 |
Yen-Chen Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090184656 | BACKLIGHT SYSTEM HAVING A LAMP CURRENT BALANCE AND FEEDBACK MECHANISM AND RELATED METHOD THEREOF - A lamp current balance and feedback system and related method are disclosed for balancing the input and output currents of a lamp by making use of a lamp current balance and feedback mechanism. The operation of the lamp current balance and feedback mechanism includes coupling the input current of the lamp for generating a first balance current by a first transformer, coupling the output current of the lamp for generating a second balance current by a second transformer, coupling the first and second transformers for substantially equalizing the first and second balance currents, generating a feedback signal based on the first or second balance current by a feedback circuit, generating a pulse width modulation signal based on the feedback signal by a pulse width modulation signal generation circuit, and driving the input and output currents of the lamp based on the pulse width modulation signal by a driving circuit. | 07-23-2009 |
Yen-Liang Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110157071 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of floating gate type ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each floating gate type ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
| 20110157084 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of diode ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each diode ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
Yi-Chen Huang, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 12-18-2008 |
Yi-Chih Huang, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090153791 | Chip on film structure - The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge. | 06-18-2009 |
Zi-Long Huang, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110068831 | LOW POWER LINE DRIVER AND METHOD THEREOF - A line driver for a communications system requiring multiple power sources for different modes of operation comprises a current source and a voltage source coupled in parallel with the current source. The current source has a first terminal and a second terminal. The line driver further comprises a first source resistor coupled to the first terminal of the current source and a second source resistor coupled to the second terminal of the current source. The current source provides a driving current and the voltage source provides a driving voltage at the same time during operations of the communications system. | 03-24-2011 |
| 20110075741 | MULTIMODE ETHERNET LINE DRIVER - A multimode line driver circuit is provided. The multimode line driver circuit has a first driver circuit for receiving a first differential input signal and transmitting a first differential output signal, and a second driver circuit for receiving a second driver circuit for receiving a second differential input signal and transmitting a second differential output signal. The multimode line driver circuit also has a first switch coupling the first driver circuit to a first power supply and a second switch coupling the second driver circuit to a second power supply. The multimode line driver circuit also has a transformer coupled to the output interface for transforming the first differential output and the second differential output and a mode controller configured to close the first switch in the first mode and to close the second switch in the second mode. | 03-31-2011 |
| 20110163807 | IMPEDANCE MATCHING CIRCUIT AND METHOD THEREOF - A circuit comprises an amplifier circuit and a trimming circuit. The amplifier circuit includes an operational amplifier. The operational amplifier has a first input configured to receive input signals, and the operational amplifier also has a second input and an amplifier output. One of the first input or the second input is a negative input. The trimming circuit is coupled to the amplifier output. The trimming circuit includes a termination resistor coupled in parallel with at least one trimming resistor. The termination resistor is coupled to a first switch in series, and the trimming resistor is coupled to a second switch in series. The amplifier output is connected back to the negative input through the first switch. | 07-07-2011 |
