Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Hua, TX
Binh Hua, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090199216 | MULTI-LEVEL DRIVER CONFIGURATION - A method, medium and implementing processing system are provided in which the Operating System (OS) driver is divided into two parts, viz. an upper level OS driver and a lower level OS driver. The lower level OS driver sets up the adapter hardware and any adapter hardware work-around. The upper level OS driver is interfaced to the OS communication stack and each can be compiled separately. The upper OS driver is compiled and shipped with the OS to make sure it is compatible with the OS communication stack. The lower OS driver, in an exemplary embodiment, is compiled and stored in an adapter flash memory. The OS dynamically combines the upper and lower OS drivers together during the load time. | 08-06-2009 |
| 20100318666 | EXPEDITING ADAPTER FAILOVER - Expediting adapter failover may minimize network downtime and preserve network performance. Embodiments may comprise copying a primary adapter memory of a failing primary adapter to a standby adapter memory of a standby adapter. Copying the memory may expedite TCP/IP offload adapter failover by maintaining TCP/IP stack and connection information. In several embodiments, Copy Logic may copy primary adapter memory to standby adapter memory. In some embodiments, Detect Logic may monitor primary adapter viability and may initiate failover. In additional embodiments, Assess Logic may assess whether the IO bus is operative permitting Direct Logic to copy adapter memory via, e.g., DMA. In other embodiments, Packet Logic may fragment primary adapter memory into network packets sent through the network to the standby adapter where Unpack Logic may unpack them into memory. | 12-16-2010 |
Chanh V. Hua, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090029582 | Tamper-Evident Connector - Embodiments of a tamper-evident connector are disclosed which may optionally be used in a trusted computing environment. In an exemplary embodiment, a tamper-evident connection includes a mate-once engaging assembly for providing with a first component, the mate-once engaging assembly including a foldable portion. The tamper-evident connection also includes a receiving chamber for providing with a second component, the mate-once engaging assembly fitting in the receiving chamber to physically secure the first component to the second component, the foldable portion of the mate-once engaging assembly unfolding during removal of the mate-once engaging assembly from the receiving chamber to provide evidence of tampering when the first component has been removed from the second component. Optionally, the first component is a Trusted Platform Module (TPM) and the second component is a system board. | 01-29-2009 |
| 20100081311 | Tamper-Evident Connector - Embodiments of a tamper-evident connector are disclosed which may optionally be used in a trusted computing environment. In an exemplary embodiment, a tamper-evident connection includes a mate-once engaging assembly for providing with a first component, the mate-once engaging assembly including a foldable portion. The tamper-evident connection also includes a receiving chamber for providing with a second component, the mate-once engaging assembly fitting in the receiving chamber to physically secure the first component to the second component, the foldable portion of the mate-once engaging assembly unfolding during removal of the mate-once engaging assembly from the receiving chamber to provide evidence of tampering when the first component has been removed from the second component. Optionally, the first component is a Trusted Platform Module (TPM) and the second component is a system board. | 04-01-2010 |
Hong Hua, Austin, TX US
Hong L. Hua, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090300211 | REDUCING IDLE TIME DUE TO ACKNOWLEDGEMENT PACKET DELAY - Mechanisms for reducing the idle time of a computing device due to delays in transmitting/receiving acknowledgement packets are provided. A first data amount corresponding to a window size for a communication connection is determined. A second data amount, in excess of the first data amount, which may be transmitted with the first data amount, is calculated. The first and second data amounts are then transmitted from the sender to the receiver. The first data amount is provided to the receiver in a receive buffer of the receiver. The second data amount is maintained in a switch port buffer of a switch port without being provided to the receive buffer. The second data amount is transmitted from the switch port buffer to the receive buffer in response to the switch port detecting an acknowledgement packet from the receiver. | 12-03-2009 |
| 20100318666 | EXPEDITING ADAPTER FAILOVER - Expediting adapter failover may minimize network downtime and preserve network performance. Embodiments may comprise copying a primary adapter memory of a failing primary adapter to a standby adapter memory of a standby adapter. Copying the memory may expedite TCP/IP offload adapter failover by maintaining TCP/IP stack and connection information. In several embodiments, Copy Logic may copy primary adapter memory to standby adapter memory. In some embodiments, Detect Logic may monitor primary adapter viability and may initiate failover. In additional embodiments, Assess Logic may assess whether the IO bus is operative permitting Direct Logic to copy adapter memory via, e.g., DMA. In other embodiments, Packet Logic may fragment primary adapter memory into network packets sent through the network to the standby adapter where Unpack Logic may unpack them into memory. | 12-16-2010 |
| 20110153931 | HYBRID STORAGE SUBSYSTEM WITH MIXED PLACEMENT OF FILE CONTENTS - A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD. | 06-23-2011 |
Hong Lam Hua, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080232349 | Optimization of Network Adapter Utilization in EtherChannel Environment - Method, system and computer program product for transferring data in a data processing system network. A method for transferring data in a data processing system network according to the invention includes determining an adapter among a plurality of adapters that has the lowest transmit latency, and assigning data to be transferred to the adapter determined to have the lowest transmit latency. The data to be transferred is then transferred by the assigned adapter. The present invention utilizes network adapters to transfer data in a more efficient manner. | 09-25-2008 |
| 20090199216 | MULTI-LEVEL DRIVER CONFIGURATION - A method, medium and implementing processing system are provided in which the Operating System (OS) driver is divided into two parts, viz. an upper level OS driver and a lower level OS driver. The lower level OS driver sets up the adapter hardware and any adapter hardware work-around. The upper level OS driver is interfaced to the OS communication stack and each can be compiled separately. The upper OS driver is compiled and shipped with the OS to make sure it is compatible with the OS communication stack. The lower OS driver, in an exemplary embodiment, is compiled and stored in an adapter flash memory. The OS dynamically combines the upper and lower OS drivers together during the load time. | 08-06-2009 |
Ling Hua, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090004720 | Smart Biocatalysts For Organic Synthesis - The present disclosure relates to compositions, systems, and methods that include a reusable biocatalyst. A reusable biocatalytic composition may include a stimulus-responsive support operable to be soluble under at least one first condition and insoluble under at least one second condition; and a biocatalyst bound to the stimulus-responsive support complex. According to some embodiments, a method for catalyzing a reaction may include contacting a first reactant with a composition comprising a stimulus-responsive support, a biocatalyst linked to the stimulus-responsive support, and a first solvent under conditions in which the stimulus-responsive support is soluble in the solvent and the reactant is converted to a product. A reusable biocatalyst system, in some embodiments, may include (a) a stimulus-responsive support; (b) a biocatalyst (i) bound to the stimulus-responsive support complex and (ii) having catalytic activity in the presence of a substrate; and a solvent operable to support both first and second condition. | 01-01-2009 |
| 20100137636 | IDENTIFICATION OF A NITRILASE FROM B. JAPONICUM BY RATIONAL GENOME MINING AND METHODS OF USE - The present disclosure relates to methods of rational genome mining. A method may include narrowing the number of clones that would otherwise need to be screened and/or identifying a gene with a desired catalytic activity. The disclosure also relates to a nitrile hydrolase from | 06-03-2010 |
| 20100267100 | Enzymatic synthesis of optically pure beta-hydroxy carboxylic acids and their derivatives - The present disclosure is related to systems, compositions, and methods for producing a β-hydroxy carboxylic acid and/or a β-hydroxy carboxylic amide in enantiomeric excess (e.g., enantiomerically pure). In some specific example embodiments, a method may include contacting a substrate and/or intermediate with a cyanide, a ketoreductase, a nitrilase, and/or a nitrile hydratase. Systems, compositions, and methods, in some embodiments, may produce a β-hydroxy carboxylic acid and/or a β-hydroxy carboxylic amide in enantiomeric excess under convenient conditions (e.g., pH 5-9 and temperatures under 50° C.). | 10-21-2010 |