| Patent application number | Description | Published |
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| 20090155965 | METHOD OF FABRICATING A NON-FLOATING BODY DEVICE WITH ENHANCED PERFORMANCE - Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region. | 06-18-2009 |
| 20100176424 | Doping of Semiconductor Fin Devices - A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface. | 07-15-2010 |
| 20100177289 | Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography - An immersion lithographic system | 07-15-2010 |
| 20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 04-05-2012 |
| Patent application number | Description | Published |
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| 20080217047 | CIRCUIT BOARD SURFACE STRUCTURE - A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element. | 09-11-2008 |
| 20080272501 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 11-06-2008 |
| 20090050359 | Circuit board having electrically connecting structure and fabrication method thereof - A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer. | 02-26-2009 |
| 20090134515 | SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads. | 05-28-2009 |
| 20110031617 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 02-10-2011 |
| 20110056738 | PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A package substrate and a manufacturing method thereof are provided, including: forming a solder mask on a package substrate body having a plurality of conductive pads; forming a plurality of first-step openings in the solder mask by exposure and development; forming a plurality of second-step openings in the solder mask by a laser-based or plasma-based drilling process; and removing a solder mask foot from the bottom of each of the first-step openings so as to expose large surface areas of the conductive pads. Hence, the contact area between a conductive element and a corresponding one of the conductive pads is large enough to enhance bonding and electrical connection therebetween. | 03-10-2011 |
