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Hsueh, CA
Aaron J.w. Hsueh, Stanford, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090298770 | MAMMALIAN RELAXIN RECEPTORS - High affinity relaxin receptors, polypeptide compositions related thereto, as well as nucleotide compositions encoding the same, are provided. These proteins, herein termed LGR7 and LGR8, are orphan leucine-repeat-containing, G protein-coupled receptors. These receptors have a wide and a unique tissue expression pattern. The receptors, particularly soluble fragments thereof, are useful as therapeutic agents capable of inhibiting the action of relaxin and InsL3. The receptors and fragments thereof also find use in the screening and design of relaxin agonists and antagonists. Conditions treatable with relaxin agonists or antagonists include prevention or induction of labor, treatment of endometriosis, treatment of skin conditions such as scleroderma that require collagen or extracellular matrix remodelling. Additionally, relaxin has been implicated in the dilation of blood vessels' smooth muscle cells directly and through release of nitric oxide and atrial natriuretic peptide. Relaxin has also been used in the treatment of severe chronic pain, particularly pain arising from stretching, swelling, or dislocation of tissues. | 12-03-2009 |
| 20100191040 | Manipulation of ovarian primordial follicles - Methods are provided for activating dormant ovarian primordial follicles in a mammal to promote development to preovulatory follicles. | 07-29-2010 |
| 20110052599 | Facilitation of Oocyte, Zygote and Pre-Implantation Embryo Maturation - Compositions and methods are provided for enhancing the survival and promoting the maturation of mammalian oocytes, zygotes and preimplantation embryos. BDNF or BDNF agonists may be administered to an individual, or to cells in vitro, to enhance cellular maturation, embryo growth and fertilization. Accordingly, compositions comprising BDNF are herein presented for use in promoting in vivo oocyte maturation as well as for use as a component in culture media for promoting preimplantation maturation of zygotes and embryos, for instance, for use with in vitro fertilization procedures and for the production of stem cells. Additionally, compounds that interfere with the binding of BDNF to its receptor may be administered to an individual to prevent oocyte maturation, thereby acting as a contraceptive. The BNDF receptor, TrkB, and BDNF also find use in the screening and design of agonists and antagonists for use in the methods of the invention. | 03-03-2011 |
| 20120066775 | Stresscopins and their Uses - The invention provides novel nucleic acids and polypeptides, referred to herein as stresscopin 1 and stresscopin 2, which preferentially activate the CRH-R2 receptor over the R1 receptor. Stresscopins, analogs and mimetics, and related CRH-R2 agonists suppress food intake and heat-induced edema; but do not induce substantial release of ACTH. Stresscopin also finds use in the recovery phase of stress responses, as an anti-inflammatory agent, as a hypotensive agent, as a cardioprotective agent, and in the treatment of psychiatric and anxiolytic disorders. Stresscopin nucleic acid compositions find use in identifying homologous or related proteins and the DNA sequences encoding such proteins; in producing compositions that modulate the expression or function of the protein; and in studying associated physiological pathways. | 03-15-2012 |
Angela M. Hsueh, Diamond Bar, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100059455 | METHODS AND SYSTEMS FOR DISINFECTING POTABLE WATER SUPPLIES - The invention described herein contains two aspects, usable together or separately, that address the needs in the art described above, namely a first aspect that relates to the provision of a transportable water purification system that can be contained on a passenger transport vehicle, and that can use, but does not require, continuous, real-time monitoring, and a second aspect that relates to the use of UV purification of the water as it is uploaded to the passenger transport vehicle after a single pass through the UV chamber. | 03-11-2010 |
Chih Hsueh, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090158085 | POWER SAFE TRANSLATION TABLE OPERATION IN FLASH MEMORY - Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error. | 06-18-2009 |
| 20090164700 | EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN - Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component. | 06-25-2009 |
John Hsueh, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110075994 | System and Method for Video Storage and Retrieval - A method and system for providing functionality similar to that found in a DVR but mostly or completely contained within a television set is disclosed. A memory stores packets representing a portion of one or more programs in the broadcast stream and allows a viewer to replay that portion of the program using some of the functions available on a DVR, such as pause, rewind, and fast forward. The packet stream is divided into groups of equal length and fixed time duration, for example one second, and stored in sequential order in the memory. This allows for the storage and retrieval of content without the need for an index file, without adding a timestamp to the program data packets, and without separating the audio portion from the video portion of the program and then having to synchronize and recombine them. | 03-31-2011 |
Kuey-Lung Hsueh, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080316661 | Electrostatic Discharge Immunizing Circuit without Area Penalty - A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp. | 12-25-2008 |
Kyai Hsueh, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110190862 | STENT DELIVERY SYSTEM - A stent delivery system comprises a stent having a first connector disposed on a stent proximal end, and a pusher wire having a second connector disposed on a pusher wire distal end, wherein the first and second connectors are configured to releasably attach to each other. | 08-04-2011 |
Paul Hsueh, Concord, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080235939 | Manufacturing Method For Micro-SD Flash Memory Card - A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCB regions arranged in parallel rows. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded layer is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The panel is then singulated using one of a laser cutting method, an abrasive water jet cutting method, and a mechanical grinding method such that the resulting PCB substrate and plastic housing have the width, height and length specified by MicroSD specifications. A front edge chamfer process is then performed. | 10-02-2008 |
| 20090203168 | Manufacturing Method for a Secure-Digital (SD) Flash Card with Slanted Asymmetric Circuit Board - A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. | 08-13-2009 |
Philip Hsueh, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110157648 | Data Pump For Printing - Systems and techniques for printing on a workpiece. In one implementation, a data pump is used to create a packet of image data for a print head assembly. The data pump includes multiple state machines to receive image data from an image buffer on a computer, and a serializer to gather image data from each of the state machines. Each of the state machines is configured to send image data to the serializer at a different instance in time. The serializer is configured to arrange the gathered image data according to when the serializer received the image data from each of the state machines. The data pump also includes an optical fiber communication interface to connect with a communication channel. | 06-30-2011 |
Rex Hsueh, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100306448 | CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE - A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted. | 12-02-2010 |
Sheng-Hsiung Hsueh, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090052248 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 02-26-2009 |
| 20090067239 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 03-12-2009 |
| 20090323415 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 12-31-2009 |
| 20110122693 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 05-26-2011 |
Steve Hsueh, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120030469 | Streamlined CSR Generation, Certificate Enrollment, and Certificate Delivery - The process of acquiring SSL certificates for enterprise SSL customers is improved by reducing the number of steps used to acquire the SSL certificate and streamlining the process. An on-line CSR generator on the certificate enrollment form is used to submit the customer information (i.e. Common Name, Organizational Unit, Organization, City/Locality, State/Province, and Country Code) and generate the CSR. By making the CSR generation part of the enrollment process, the administrator can use the same enrollment form to submit the customer information along with the contact information pertinent to the enterprise. | 02-02-2012 |
Walter C. Hsueh, San Mateo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120102553 | Mixed-Mode Authentication - Techniques for mixed-mode authentication are described. In one or more embodiments, an authentication service may be implemented to selectively configure and issue authentication tokens based upon an optional secure mode that enables enhanced security. Clients may be provided with an option to choose between an insecure mode and a secure mode for authentications. Based on this choice, tokens may be configured to include an indication of whether the secure mode is disabled or enabled. When secure mode is disabled, an insecure token valid for both secure sites and other sites is issued to a client when the client is authenticated. When the optional secure mode is enabled, both secure and insecure tokens are provided to the client. The authentication services and/or other services may be configured to reject an insecure token when secure mode is enabled to prevent unauthorized use of a stolen token to access secure resources. | 04-26-2012 |
Wayne Y.w. Hsueh, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110223729 | INTEGRATED CIRCUIT INCLUDING POWER DIODE - A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode. | 09-15-2011 |
Yu-Li Hsueh, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090074123 | Phase/Frequency Detector and Charge Pump Architecture for Referenceless Clock and Data Recovery (CDR) Applications - A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P | 03-19-2009 |
| 20090208226 | Bang-bang architecture - In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed. | 08-20-2009 |