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Hsue
Ching-Wen Hsue, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110006962 | POROUS MAGNETIC ANTENNA - The present invention relates to a porous magnetic antenna, comprising: an antenna; an insulating layer, having one side next to said antenna; and a magnetic layer, placed next to the other side of the insulating layer, separated from said antenna with a distance, and having at least one hole. The porous magnetic antenna has the advantages of shaping the field pattern, lowering the sensitivity, improving the gain value and possessing stable directionality. | 01-13-2011 |
Ching-Wen Hsue, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100245199 | MAGNETIC ANTENNA - A magnetic antenna is provided. The magnetic antenna includes an antenna; and a magnetic piece configured near the antenna with a distance therebetween. | 09-30-2010 |
Hong-June Hsue, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120134360 | DEVICE AND METHOD FOR PROCESSING NETWORK PACKET - A device for processing a network packet includes a capturing unit, a look-up table supplying unit, a preprocessing unit and a control unit. The capturing unit is utilized for capturing an information from the network packet. The look-up table supplying unit is utilized for supplying a look-up table. The preprocessing unit is coupled to the capturing unit and the look-up table supplying unit, for comparing the information with the look-up table to generate a comparison result. The control unit is coupled to the preprocessing unit, for choosing a processing rule to process the network packet according to the comparison result. | 05-31-2012 |
Jei Way Hsue, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100254303 | WIRELESS INTERMEDIARY DEVICE AND WIRELESS TRANSMISSION METHOD - The invention provides a wireless intermediary device and a wireless transmission method. The wireless intermediary device includes a processing module and a plurality of transmission interfaces. Each transmission interface is used for transmitting the data units by a corresponding transmission media frequency, respectively. The processing module distributes the data units to the transmission interfaces according to a distribution principle to transmit the data units. The wireless intermediary device and the wireless transmission method utilize a plurality of wireless systems to increase the available bandwidth. Consequently, the transmission speed is higher, the transmission distance is longer, and multi-layer service application and high quality multimedia stream are provided. | 10-07-2010 |
Jin-Jen Hsue, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100100919 | METHOD FOR REDUCING UPSTREAM INGRESS NOISE IN CABLE DATA SYSTEM - In a method of reducing and diagnosing upstream ingress noise in cable data system utilize a MAC/MAP management messages via a downstream path based on Cable Systems Interface Specification (DOCSIS) to provide precise control of gates deployed near the user side provide a powerful algorithm for CATV operators to mitigate ingress noise problem. | 04-22-2010 |
Tzeng Ju Hsue, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100172188 | METHOD FOR CONDUCTING OVER-ERASE CORRECTION - A method for conducting an over-erase correction comprises the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation. | 07-08-2010 |
| 20120008421 | DATA OUTPUTING METHOD OF MEMORY CIRCUIT AND MEMORY CIRCUIT AND LAYOUT THEREOF - A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6. | 01-12-2012 |