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| 20100162036 | Self-Monitoring Cluster of Network Security Devices - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 06-24-2010 |
| 20100162383 | Cluster Architecture for Network Security Processing - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 06-24-2010 |
| 20100169446 | Cluster Architecture and Configuration for Network Security Devices - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 07-01-2010 |
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| 20080252352 | System and Method for Using a DLL for Signal Timing Control in an eDRAM - The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined delay from the clock signal, and at least one DRAM array coupled to the plurality of control signals, wherein the DRAM array operates in a plurality of steps controlled by the plurality of control signals. | 10-16-2008 |
| 20100214857 | MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF - An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell. | 08-26-2010 |
| 20100253303 | VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO - A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed. | 10-07-2010 |
| 20100328982 | CONTENT ADDRESSABLE MEMORY DESIGN - A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries. | 12-30-2010 |
| 20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 12-30-2010 |
| 20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
| 20120026805 | SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION - An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level. | 02-02-2012 |
| 20120038410 | CIRCUIT AND METHOD FOR CHARACTERIZING THE PERFORMANCE OF A SENSE AMPLIFIER - An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current. | 02-16-2012 |
| 20120081165 | HIGH VOLTAGE TOLERATIVE DRIVER - A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS. | 04-05-2012 |
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| 20090077133 | SYSTEM AND METHOD FOR EFFICIENT RULE UPDATES IN POLICY BASED DATA MANAGEMENT - A method, system, and computer program product is provided for efficient policy rule update in a data management system. A policy rule is stored along with the attributes of a data object when the application of the policy rule results in action taken on the data object. A stored policy rule, called an effective policy rule, is subsequently used to restrict the number of data objects examined when a policy rule is added, deleted, modified, or otherwise updated. | 03-19-2009 |
| 20090112843 | SYSTEM AND METHOD FOR PROVIDING DIFFERENTIATED SERVICE LEVELS FOR SEARCH INDEX - Programs, systems and methods for providing differentiated service levels for a search index are disclosed. Data object documents are processed by extracting terms and scoring each of the terms associated with each document according to criteria to indicate relative importance of the associated document. A plurality of posting lists are generated for each term each comprising entries identifying documents that include the term. The entries are allocated to the different posting lists for the given term depending upon the score for the term associated with particular document. The different posting lists, e.g. a high score and low score posting list, may then be stored as data objects managed according to their indicated importance. For example, the high score posting list data object may be stored in higher performance storage than the low score posting list data object. Scores may be regularly updated. | 04-30-2009 |
| 20090125884 | SYSTEM AND METHOD FOR WORKFLOW-DRIVEN DATA STORAGE - Programs, systems and methods are described for efficiently storing data as used under a workflow-driven model. A workflow process is defined to control the processing of data objects through different states, e.g., such as an insurance claim document passing through different stages of processing. The workflow process is modeled and employed to manage the storage system based upon predicted state changes derived from state statistics that can be applied to enhance efficiency. For example, copies of the data object may be automatically made when the data object is expected to change state. Some anticipated states implicating high access may direct a storage location with low access time. Hints or requirements for the data object may be applied upon occurrence of an expected state change. Storage management of expected state changes may be further enhanced through dynamic adjustment of the state statistics using collected historical state information to further enhance efficiency. | 05-14-2009 |
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| 20090049003 | SYSTEM AND METHOD FOR PROVIDING WRITE-ONCE-READ-MANY (WORM) STORAGE - Techniques for providing write-once-read-many (WORM) storage are described herein. According to one embodiment, a range of values is received to set an attribute of a file, where the received range of values is outside of an ordinary range of the attribute in accordance with a file system associated with the file. In addition, a management action is received to be associated with the received range of values of the attribute, where the management action is unrelated to an ordinary action associated with the attribute of the file in accordance with the file system. In response, the received management action is associated with the received range of values of the attribute. Other methods and apparatuses are also described. | 02-19-2009 |
| 20100049735 | METHOD AND APPARATUS FOR MANAGING DATA OBJECTS OF A DATA STORAGE SYSTEM - Techniques for managing data objects of a data storage system are described herein. According to one embodiment, a perfect hash function is generated for data objects stored in a data storage system. For each of the data objects, a hash operation is performed using the perfect hash function to indicate whether the respective data object is alive. Resources associated with the respective data object is reclaimed if it is determined that the respective data object is not alive based on a result of the hash operation using the perfect hash function, where the reclaimed resources are released back to the data storage system as free resources. Other methods and apparatuses are also described. | 02-25-2010 |
| 20100332452 | System and method for providing long-term storage for data - A system for storing files comprises a processor and a memory. The processor is configured to break a file into one or more segments; store the one or more segments in a first storage unit; and add metadata to the first storage unit so that the file can be accessed independent of a second storage unit, wherein a single namespace enables access for files stored in the first storage unit and the second storage unit. The memory is coupled to the processor and configured to provide the processor with instructions | 12-30-2010 |
| 20110238714 | System and Method for Providing Write-Once-Read-Many (WORM) Storage - Techniques for providing write-once-read-many (WORM) storage are described herein. According to one embodiment, in response to a command to set a time attribute of a file to a first predetermined value, it is determined whether the first predetermined value is outside of an ordinary range of values associated with the time attribute in accordance with a file system associated with the file. The file is designated as a WORM file and a WORM retention period is set for the file based on the first predetermined value, if the first predetermined value is outside of an ordinary range of values associated with the time attribute. The designation of the file as a WORM file and setting the WORM retention period are performed in response to the command. | 09-29-2011 |
| 20120041957 | EFFICIENTLY INDEXING AND SEARCHING SIMILAR DATA - Techniques for efficiently indexing and searching similar data are described herein. According to one embodiment, in response to a query for one or more terms received from a client, a query index is accessed to retrieve a list of one or more super files. Each super file is associated with a group of similar files. Each super file includes terms and/or sequences of terms obtained from the associated group of similar files. Thereafter, the super files representing groups of similar files are presented to the client, where each of the super files includes at least one of the queried terms. Other methods and apparatuses are also described. | 02-16-2012 |
