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| 20090116244 | LIGHT-EMITTING MODULE - A light-emitting module includes a substrate having a first surface and a second surface, at least one light-emitting device disposed on the first surface of the substrate, and an optical reflection layer disposed on the first surface of the substrate and surrounding the light-emitting device for receiving a portion of light emitted from the light-emitting device and reflecting the portion of light. The substrate can be rigid or flexible. | 05-07-2009 |
| 20090152741 | CHIP STRUCTURE AND FABRICATION PROCESS THEREOF AND FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF - A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has at least one first opening, wherein the first opening correspondingly exposes the bonding pad. The first conductive layer covers an inner wall of the first opening and the bonding pad so as to form a concave structure in the first opening. When the chip structure is bonded to a substrate, the solder bump of the substrate is inlaid into the concave structure of the chip. Moreover, a fabrication process of the chip structure, a flip chip package structure and a fabrication process thereof, a package structure of a light emitting/receiving device and a chip stacked structure are also provided. | 06-18-2009 |
| 20090311810 | METHOD OF MANUFACTURING BENDABLE SOLID STATE LIGHTING - The invention provides a method of manufacturing a bendable solid state lighting (SSL). A first metal layer and a second metal layer with a predetermined circuit layout pattern and structure region pattern are first deposited on both sides of a flexible substrate respectively, where a plurality of bonding pads is formed on the structure regions in the structure region pattern and is used for being electrically connected to the first metal layer. A plurality of LED dies is arranged on the structure regions in an array, and the LED dies are bonded with the corresponding bonding pads, such that the LED dies are conducted with current via the circuit layout of the first metal layer on the flexible substrate, so as to form a planar light source. | 12-17-2009 |
| 20100163897 | FLEXIBLE LIGHT SOURCE DEVICE AND FABRICATION METHOD THEREOF - A flexible light source device including a substrate, a light emitting device, a molding compound, a dielectric layer, and a metal line is provided. The substrate has a first surface, a second surface opposite to the first surface, and a first opening. The light emitting device is disposed on the first surface of the substrate and covers the first opening. The molding compound is located above the first surface and covers the light emitting device. The dielectric layer is disposed on the second surface and covers a sidewall of the first opening. The dielectric layer has a second opening which exposes part of the light emitting device. The metal line is disposed on the dielectric layer, wherein the metal line is electrically connected to the light emitting device via the second opening in the dielectric layer. Additionally, a fabrication method of the flexible light source device is also provided. | 07-01-2010 |
| 20120140464 | FLEXIBLE LIGHT SOURCE MODULE - A flexible light source module including a flexible substrate, a flexible light guide film and a plurality of point light sources is provided. The flexible light guide film including light-guiding portions is disposed on the point light sources. Each of the light-guiding portions includes a light incident surface and a light emitting surface. The light incident surface includes light incident sub-surfaces. The light emitting surface includes light emitting sub-surfaces, and the one closest to the geometric center of the light-guiding portion is a first light emitting sub-surface. The absolute values of the tangent slopes of the first light emitting sub-surface are ascending with approaching the geometric center of the light-guiding portion. The light beams emitted from the point light sources exit out of the flexible light source module via the flexible light guide film so that the flexible light source module provides a uniform planar light source. | 06-07-2012 |
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| 20080237809 | METHOD OF FABRICATING HYBRID ORIENTATION SUBSTRATE AND STRUCTURE OF THE SAME - A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed. | 10-02-2008 |
| 20090242997 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 10-01-2009 |
| 20100327378 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area. | 12-30-2010 |
| 20110031558 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE - A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer. | 02-10-2011 |
| 20110034019 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 02-10-2011 |
| 20110189827 | METHOD OF FABRICATING EFUSE STRUCTURE, RESISTOR STURCTURE AND TRANSISTOR STURCTURE - A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess. | 08-04-2011 |
| 20110294287 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate. | 12-01-2011 |
| 20120070952 | REMOVING METHOD OF A HARD MASK - A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate. | 03-22-2012 |
| 20120088368 | METHOD OF SELECTIVELY REMOVING PATTERNED HARD MASK - A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask. | 04-12-2012 |
| 20120244669 | Method of Manufacturing Semiconductor Device Having Metal Gates - The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench. | 09-27-2012 |
| 20120256276 | Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O | 10-11-2012 |
| 20120322218 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening. | 12-20-2012 |
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| 20100302981 | METHOD AND APPARATUS FOR ROAMING IN A WIRELESS NETWORK - An apparatus for roaming in a wireless network updates received signal strength indication (RSSI) values in accordance with all types of frames forwarded from the access point with which the apparatus associates. In addition, the apparatus actively forwards null frames to the access point with which the apparatus associates and updates RSSI values in accordance with acknowledgement frames forwarded from the access point. | 12-02-2010 |
| 20100302982 | METHOD FOR RECEIVING PACKETS AND APPARATUS FOR USING THE SAME - An apparatus utilizes different channels for forwarding notification packets to at least one station and an access point. The station and the access point start or stop forwarding packets to the apparatus according to the notification packets. The station and the access point also temporarily store the packets to be forwarded to the apparatus and forward the packets to the apparatus after receiving a start notification packet from the apparatus. | 12-02-2010 |
| 20110051693 | METHOD AND APPARATUS FOR ROAMING SEAMLESSLY - In accordance with the invention, a method for roaming seamlessly comprises the steps of: associating with a first access point; selecting a second access point if a first received signal strength indication (RSSI) value is less than a first threshold value; performing an authentication procedure and a handshaking procedure with the second access point; and associating with the second access point if a second RSSI value is less than a second threshold value. | 03-03-2011 |
| 20110064080 | METHOD FOR WLAN LINK AGGREGATION AND SYSTEM FOR USING THE SAME - A system with WLAN link aggregation comprises an access point, a station and a remote host. The station is equipped with a first network interface unit and a second network interface unit. The first network interface unit and the second network interface unit are configured to forward packets to or receive packets from the access point. After receiving packets from the first network interface unit, the second network interface unit or the remote host, the access point modifies headers of the packets and forwards the packets to the first network interface unit, the second network interface unit or the remote host. | 03-17-2011 |
| 20110205921 | METHOD AND APPARATUS FOR GENERATING FORBIDDEN CHANNEL LIST - A method for generating a forbidden channel list for a combined wireless communication station comprises the steps of: obtaining a channel usage report from an access point; performing a channel scan procedure; generating at least one of a channel load report, a noise indicator report, a signal strength indicator report and a packet error rate report according to the results of the channel scan procedure; and generating a forbidden channel list at least according to the generated one of the channel usage report, the channel load report, the noise indicator report, the signal strength to report, and the packet error rate report. | 08-25-2011 |
| 20120330627 | METHOD AND COMPUTER READABLE MEDIA FOR DETERMINING ORIENTATION OF FIBERS IN A FLUID - One aspect of the present invention provides a method for determining orientation of fibers in a fluid having polymer chains, characterized in that the determining of the orientation of the fibers is performed by taking into consideration an interaction between the fibers and the fluid, wherein the interaction between the fibers and the fluid comprises changes in configuration of the polymer chain to cause the entanglement or adsorption between the fibers and the polymer chains. Another aspect of the present invention provides a method for determining orientation of fibers in a fluid having polymer chains, the fibers in the fluid including a transitional movement and a rotatory movement, the method being characterized in that the determining of the orientation of the fibers is performed by taking into consideration a steric barrier effect on a rotary movement of the fibers. | 12-27-2012 |
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| 20090259896 | BAD BLOCK IDENTIFYING METHOD FOR FLASH MEMORY, STORAGE SYSTEM, AND CONTROLLER THEREOF - A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged. | 10-15-2009 |
| 20090259916 | DATA ACCESSING METHOD, CONTROLLER AND STORAGE SYSTEM USING THE SAME - Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command. | 10-15-2009 |
| 20110191525 | FLASH MEMORY STORAGE DEVICE, CONTROLLER THEREOF, AND DATA PROGRAMMING METHOD THEREOF - A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks. | 08-04-2011 |
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| 20090256619 | HIGH-SIDE DRIVER - A high-side driving circuit is provided, where Q terminal and | 10-15-2009 |
| 20110062907 | APPARATUS AND METHOD FOR DRIVING SENSORLESS MOTOR - An apparatus and a method for driving a sensorless motor are described and shown in the specification and drawings, where the method includes steps as follows. First, a control signal is acquired, where the control signal has information of a predetermined rotational speed. Next, energy is supplied and progressively increased to the sensorless motor, so as to rotate a rotor of the sensorless motor. Then, a position of the rotor is detected. Finally, the energy is gradually regulated so that the sensorless motor is maintained at the predetermined rotational speed. | 03-17-2011 |
| 20110074322 | APPARATUS AND METHOD FOR DETECTING LOCK ERROR IN SENSORLESS MOTOR - An apparatus and a method for detecting a lock error in a sensorless motor are disclosed, where the apparatus includes a multiplexer, a negative booster, a comparator and a timer. The multiplexer can receive a coil voltage from the sensorless motor. The negative booster can receive a neutralizing voltage from the sensorless motor and drop the neutralizing voltage. The comparator can compare the coil voltage with the dropped neutralizing voltage for outputting a zero-crossing signal. The timer can count time duration during the zero-crossing signal maintained at the a logic level and determine the lock error in the sensorless motor when the time duration exceeds a predetermined period. | 03-31-2011 |
| 20110241588 | SYSTEM AND METHOD FOR CONTROLLING SENSORLESS MOTOR - A system and a method for controlling a sensorless motor are disclosed, where the system includes a motor driver and a zero crossing detector. The motor driver can drive the sensorless motor. The zero crossing detector can detect a zero-crossing point when the voltage of one motor coil of the sensorless motor is in a blanking period. | 10-06-2011 |
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| 20090212355 | Metal-Oxide-Semiconductor Transistor Device and Method for Making the Same - A metal-oxide-semiconductor transistor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer, and a shallow junction well formed on the two lateral sides of the gate structure including a source region and a heavy doping region. The gate structure includes a conductive layer having a gap on top of the sidewall of the conductive layer and a spacer formed on the gap. | 08-27-2009 |
| 20090236636 | Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions - A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material. | 09-24-2009 |
| 20100176444 | POWER MOSFET AND METHOD OF FABRICATING THE SAME - A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively. | 07-15-2010 |
| 20110215397 | HIGH CELL DENSITY TRENCHED POWER SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The fabrication method of a high cell density trenched power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming at least a gate trench in a substrate with a silicon oxide patterned layer formed thereon, said silicon oxide patterned layer having at least an open aligned to the gate trench; b) forming a polysilicon gate in the gate trench; c) forming a dielectric structure in the open, the dielectric structure has a sidewall thereof being lined with an etching protection layer; d) removing the silicon oxide patterned layer by selective etching; and e) forming a spacer on a side surface of the dielectric structure to define at least a contact window. | 09-08-2011 |
| 20110266616 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 11-03-2011 |
| 20110316077 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 12-29-2011 |
| 20110318895 | FABRICATION METHOD OF TRENCHED POWER MOSFET - A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench. | 12-29-2011 |
| 20120193775 | SEMICONDUCTOR STRUCTURE WITH LOW RESISTANCE OF SUBSTRATE AND LOW POWER CONSUMPTION - A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit. | 08-02-2012 |
| 20120256258 | TRENCH POWER MOSFET STRUCTURE WITH HIGH CELL DENSITY AND FABRICATION METHOD THEREOF - A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer. | 10-11-2012 |
| 20120267713 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 10-25-2012 |
| 20120295411 | CLOSED CELL TRENCH POWER MOSFET STRUCTURE AND METHOD TO FABRICATE THE SAME - A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate. | 11-22-2012 |
| 20120309177 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 12-06-2012 |
| 20120322217 | FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH - A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region. | 12-20-2012 |
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| 20090102117 | DE-SKEW MECHANISM - A de-skew mechanism, in an image forming device, with a correcting member disposed in a rotatable manner to the rotary shaft and turning with driving roller by a spring between them. A torque spring suppresses the turning of the correcting member to correct the skew of the medium. When conveyed, the medium will butt against the correcting member to be stopped and corrected. The medium conveying force and the force that the spring brings to the driving roller are sufficient for turning the correcting member and passing therethrough. At one time, the force that the correcting member brings to the medium will reduce to zero. As such, the medium will not be damaged by the correcting member while being conveyed. | 04-23-2009 |
| 20090189338 | DE-SKEW MECHANISM - A de-skew mechanism includes a driving shaft installed on a frame of an image forming device and driven by a motor, an active roller installed on the driving shaft and driven by the driving shaft, and an idle roller driven by the active roller for driving a medium with the active roller. A nip is formed between the active roller and the idle roller. The de-skew mechanism further includes a correcting member installed on the driving shaft in a rotatable manner and located upstream of the nip for correcting skew of the medium in a correcting position, and a restoring member connected to the correcting member for loading torque to the correcting member so as to drive the connecting member from the correcting position to a releasing position where the medium pass therethrough. | 07-30-2009 |
| 20090189343 | PAPER-FEEDING MECHANISM - The paper-feeding mechanism includes a duplex drive roller disposed on a terminal end of a feeding path of an image-forming device for feeding paper and on a side of an output tray, a first idle roller for conveying the paper back to the output tray with the duplex drive roller after a single side of the paper is printed, a second idle roller for conveying the paper back to the output tray with the duplex drive roller after double sides of the paper are printed, and a stop means installed between the terminal end of the feeding path and the output tray for switching to a shut position to stop the paper when the paper is driven back to the feeding path and for switching to an open position when the paper is driven to the output tray after the double sides of the paper are printed. | 07-30-2009 |
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| 20110016263 | METHOD FOR PERFORMING DATA PATTERN MANAGEMENT REGARDING DATA ACCESSED BY A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management. | 01-20-2011 |
| 20110107141 | DATA STORAGE DEVICE, CONTROLLER, AND DATA ACCESS METHOD FOR A DOWNGRADE MEMORY - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses. | 05-05-2011 |
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| 20090308446 | BACKSIDE ELECTRODE LAYER AND FABRICATING METHOD THEREOF - A backside electrode layer and a fabricating method thereof are applicable for fabricating a solar cell. The backside electrode layer includes a first electrode layer and a second electrode layer. The first electrode layer is formed on a substrate and has a thickness smaller than 15 μm. The second electrode layer having patterns is formed on the first electrode layer. The first and second electrode layers are fabricated by a cofiring process. As the thickness of the first electrode layer is decreased and the second electrode layer is not a full coverage layer, the material usage of each electrode layer is reduced and the fabrication cost thereof is leveled down. Besides, a thinner electrode layer may avoid warp after the cofiring process. | 12-17-2009 |
| 20100098840 | METHOD OF MANUFACTURING BACK ELECTRODE OF SILICON BULK SOLAR CELL - A method of manufacturing a back electrode of a silicon bulk solar cell is provided, which includes depositing a passivation layer on a back of a silicon substrate, and then coating a first metal paste on the passivation layer. Thereafter, a first sintering is performed at a high temperature, such that the first metal paste penetrates the passivation layer, joints to the silicon substrate, and diffuses into the back of the silicon substrate. Afterward, a second metal paste is coated on the back of the silicon substrate, and then a second sintering is performed at a low temperature to cure the second metal paste without penetrating the passivation layer, so as to finish the back electrode structure. Therefore, this method can reduce the manufacturing cost and simplify the manufacturing process. | 04-22-2010 |
| 20100147374 | ELECTRODE OF SOLAR CELL AND FABRICATING METHOD THEREOF - A fabricating method of an electrode of a solar cell includes forming a first electrode layer on a photoelectric conversion layer, forming an antireflective layer on the photoelectric conversion layer to cover the first electrode layer, forming a second electrode layer on the antireflective layer, and performing a sintering process. A material of the first electrode layer does not react with the photoelectric conversion layer and the antireflective layer during the sintering process, while at least a material of the second electrode layer reacts with the antireflective layer during the sintering process. The sintering process is performed, such that the second electrode layer reacts with the antireflective layer, and the second electrode layer penetrates the antireflective layer to electrically connect the first electrode layer. | 06-17-2010 |
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| 20120267708 | TERMINATION STRUCTURE FOR POWER DEVICES - A termination structure for a power MOSFET device includes a substrate, an epitaxial layer on the substrate, a trench in the epitaxial layer, a first insulating layer within the trench, a first conductive layer atop the first insulating layer, and a column doping region in the epitaxial layer and in direct contact with the first conductive layer. The first conductive layer is in direct contact with the first insulating layer and is substantially level with a top surface of the epitaxial layer. The first conductive layer comprises polysilicon, titanium, titanium nitride or aluminum. | 10-25-2012 |
| 20120276726 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer. | 11-01-2012 |
| 20120289037 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer. | 11-15-2012 |
| 20120292687 | SUPER JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit. | 11-22-2012 |
| 20120295410 | METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer. | 11-22-2012 |
| 20120306006 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer. | 12-06-2012 |
| 20130043528 | Power transistor device and fabricating method thereof - The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer. | 02-21-2013 |
| 20130082324 | LATERAL STACK-TYPE SUPER JUNCTION POWER SEMICONDUCTOR DEVICE - A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure. | 04-04-2013 |
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| 20090196150 | Multi-stage lens driving device - A multi-stage lens driving device for driving an optical lens so as to perform the functions of zooming and/or focusing comprises: a front cover, a rear cover, a plurality of yokes, a plurality of driving coils, a lens seat, and a plurality of permanent magnets. The front cover is a hollow annular cover having a plurality of recesses formed on an inner periphery thereof and a plurality of holders on an outer periphery thereof. The rear cover can be combined with the front cover, thereby forming a receiving space therebetween. The lens seat is a hollow housing disposed in the receiving space. The yokes are provided in the recesses formed on the inner periphery of the front cover. The permanent magnets are surrounding and embedded in an outer periphery of the lens seat, disposed in correspondence to the yokes and spaced therefrom by a predetermined distance. The driving coils are provided respectively on the holders of the front cover, and correspond respectively to the yokes received in the recesses. When predetermined impulse currents of different directions are applied to the driving coils respectively, polarities of corresponding yokes are reversed, respectively. By virtue of magnetic attraction between the permanent magnets and the yokes, rotation of the lens seat in the receiving space is converted to linear axial translation. | 08-06-2009 |
| 20100195223 | Miniature magnetic-levitated lens driving device - A miniature magnetic-levitated lens driving device includes a lid, a casing, a lens module, a plate spring, and a magnetic-levitated module. The lid has a hollow structure and is coupled to the casing. The casing is formed therein with a receiving space. The lens module is provided in the receiving space. The plate spring is fixed between the lid and the casing and configured to resiliently confine the lens module to the receiving space. The magnetic-levitated module is provided in the receiving space and corresponds in position to the lens module. A magnetic repulsive force is produced by and between the magnetic-levitated module and the lens module, and in consequence the lens module is magnetically suspended in the receiving space formed by the lid and the casing, so as to save power, and minimize friction and microparticles. | 08-05-2010 |
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| 20100033144 | VOLTAGE REGULATORS - Voltage regulators are provided. In one embodiment of the voltage regulators, a differential amplifier receives a reference voltage and a feedback voltage, to generate a control signal according to a voltage difference between the feedback voltage and the reference voltage. An output transistor has a first terminal coupled to a power voltage, a control terminal coupled to the differential amplifier for receiving the control signal, and a second terminal coupled to an output terminal. A voltage feedback circuit is coupled between the output terminal and a ground voltage to generate the feedback voltage. A discharge transistor has a first terminal coupled to the ground voltage, a control terminal coupled to a first control signal, and a second terminal coupled to the output terminal through a first resistor in the voltage feedback circuit. | 02-11-2010 |
| 20100053090 | METHODS AND APPARATUS FOR DETECTING USER'S TOUCH ON A TOUCH PANEL - A method for detecting a user's touch on a touch panel includes: deriving a plurality of geometric differences of a first direction of the touch panel, wherein each of the geometric differences of the first direction represents a difference between respective coupling amounts at two locations of a plurality of locations of the first direction on the touch panel; and analyzing the geometric differences of the first direction to obtain at least one analysis result, wherein the analysis result comprises information representing whether the user touches the touch panel in one or more places. | 03-04-2010 |
| 20100073833 | CIRCUIT APPARATUS HAVING ELECTROSTATIC DISCHARGE PROTECTION FUNCTION - A circuit apparatus having an electrostatic discharge (ESD) protection function includes a first circuit module, a second circuit module, and a thick-oxide transistor. The first circuit module operates in a first power supply domain and includes at least a first transistor. The second circuit module operates in a second power supply domain different from the first power supply domain and includes at least a second transistor. The thick-oxide transistor has a control terminal for receiving a control signal, a first terminal coupled to the first circuit module, and a second terminal coupled to the second circuit module, and the thick-oxide transistor is utilized for selectively performing an ESD protection operation according to the control signal. | 03-25-2010 |
| 20100128177 | SIGNAL PROCESSING UNITS CAPABLE OF PROVIDING PLUG-IN DETECTION - Signal processing units capable of providing plug-in detection without an external circuit occupying GPIO resource are provided, in which a switching element is coupled to a television signal output pad, a terminal resistor is coupled between the switching element and a ground voltage, and an interrupt signal generator generates an interrupt signal when a receiving port of a television signal receiver is coupled to the television signal pad. A control unit turns on the switching element to connect the terminal resistor to the television signal output pad when receiving the interrupt signal, wherein the switching element, the terminal resistor, the interrupt signal generator and the control unit are integrated in a chip. | 05-27-2010 |
| 20110169466 | METHODS AND CONTROL CIRCUITS FOR CONTROLLING BUCK-BOOST CONVERTING CIRCUIT TO GENERATE REGULATED OUTPUT VOLTAGE UNDER REDUCED AVERAGE INDUCTOR CURRENT - A method of controlling a buck-boost converting circuit is provided. The buck-boost converting circuit has an inductive element, a first conduction controlling element, a second conduction controlling element, a third conduction controlling element, and a fourth conduction controlling element. The method includes: controlling the first and third conduction controlling elements to be electrically conductive and the second and fourth conduction controlling elements to be electrically nonconductive according to a first duty setting; determining a second duty setting whose generation is independent of that of the first duty setting; controlling the first and fourth conduction controlling elements to be electrically conductive and the second and third conduction controlling element to be electrically nonconductive according to the second duty setting; and controlling the second and fourth conduction controlling elements to be electrically conductive and the first and third conduction controlling elements to be electrically nonconductive according to a third duty setting. | 07-14-2011 |
| 20120326691 | VOLTAGE CONVERTER HAVING AUXILIARY SWITCH IMPLEMENTED THEREIN AND RELATED VOLTAGE CONVERTING METHOD THEREOF - A voltage converter has an input terminal and only N output terminals, and includes a DC-DC power supply block having an input node and an output node, (N+1) switches including N main output switches and an auxiliary switch each having a first end and a second end, and a switch control circuit. The DC-DC power supply block includes an inductor, and a switch module configured for alternating between a first interconnection configuration and a second interconnection configuration during a predetermined time period. First ends of the (N+1) switches are coupled to the output node, and second ends of the N main output switches are coupled to the N output terminals, respectively. The switch control circuit is configured for controlling the switch module and the (N+1) switches, wherein the (N+1) switches are switched on alternately during the predetermined time period. | 12-27-2012 |
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| 20090303974 | WIRELESS NETWORK, ACCESS POINT, AND LOAD BALANCING METHOD THEREOF - A wireless network, an access point (AP), and a load balancing method thereof are provided. Each AP of the wireless network obtains data related to bandwidth and radio frequency (RF) signal strength by interchanging messages with the other APs. Each AP performs a calculation according to the data to evaluate the advantage of potential bandwidth of the AP with respect to a user side mobile station (MS). By this advantage evaluation, one of the APs is selected to accept the association request of the MS. This method can be used to balance the load of the APs of the wireless network. | 12-10-2009 |
| 20100151859 | METHOD OF SETTING UP CONNECTION IN A COMMUNICATION SYSTEM, RADIO NETWORK CONTROLLER, AND COMMUNICATION SYSTEM - A method of setting up a connection in a communication system is provided, wherein the communication system includes a user equipment (UE). The present method includes following steps. When a first radio resource control (RRC) connection request message is received from the UE, whether the first RRC connection request message has been received before is determined. If the first RRC connection request message has been received, a first RRC connection setup message is sent back to the UE. If the first RRC connection request message has not been received, whether there is an accessible Femto access point (FAP) near the UE is further determined. If there is the accessible FAP near the UE, a first RRC connection reject message is sent back to the UE. If there is no accessible FAP near the UE, the first RRC connection setup message is sent back to the UE. | 06-17-2010 |
| 20110103303 | WIRELESS COMMUNICATION SYSTEM AND ROUTING METHOD FOR PACKET SWITCHING SERVICE, FEMTO AP USING THE ROUTING METHOD - A wireless communication system, a routing method for a packet switched service, and a Femto AP (FAP) using the routing method are provided. The wireless communication system may include a core network, a broadband IP network, a FAP and at least a user equipment (UE). The UE connects the core network through the FAP and the broadband IP network. The routing method is as follows. The FAP may evaluate a request of the packet switched service sent by the UE, and may reply an accept message to the UE. The accept message may include a FAP address. The UE may use the FAP address to send a packet switching data to the FAP in order to obtain the packet switched service. The FAP may directly conduct the packet switched service with a packet switched service supply end through the broadband IP network without routing through the core network. | 05-05-2011 |
