Patent application number | Description | Published |
20090212355 | Metal-Oxide-Semiconductor Transistor Device and Method for Making the Same - A metal-oxide-semiconductor transistor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer, and a shallow junction well formed on the two lateral sides of the gate structure including a source region and a heavy doping region. The gate structure includes a conductive layer having a gap on top of the sidewall of the conductive layer and a spacer formed on the gap. | 08-27-2009 |
20090236636 | Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions - A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material. | 09-24-2009 |
20100176444 | POWER MOSFET AND METHOD OF FABRICATING THE SAME - A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively. | 07-15-2010 |
20110215397 | HIGH CELL DENSITY TRENCHED POWER SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The fabrication method of a high cell density trenched power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming at least a gate trench in a substrate with a silicon oxide patterned layer formed thereon, said silicon oxide patterned layer having at least an open aligned to the gate trench; b) forming a polysilicon gate in the gate trench; c) forming a dielectric structure in the open, the dielectric structure has a sidewall thereof being lined with an etching protection layer; d) removing the silicon oxide patterned layer by selective etching; and e) forming a spacer on a side surface of the dielectric structure to define at least a contact window. | 09-08-2011 |
20110266616 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 11-03-2011 |
20110316077 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 12-29-2011 |
20110318895 | FABRICATION METHOD OF TRENCHED POWER MOSFET - A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench. | 12-29-2011 |
20120193775 | SEMICONDUCTOR STRUCTURE WITH LOW RESISTANCE OF SUBSTRATE AND LOW POWER CONSUMPTION - A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit. | 08-02-2012 |
20120256258 | TRENCH POWER MOSFET STRUCTURE WITH HIGH CELL DENSITY AND FABRICATION METHOD THEREOF - A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer. | 10-11-2012 |
20120267713 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 10-25-2012 |
20120295411 | CLOSED CELL TRENCH POWER MOSFET STRUCTURE AND METHOD TO FABRICATE THE SAME - A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate. | 11-22-2012 |
20120309177 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 12-06-2012 |
20120322217 | FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH - A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region. | 12-20-2012 |
20130256789 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions. | 10-03-2013 |
20130295736 | FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE - A fabrication method of a trench power semiconductor structure is provided. First, a substrate with a first epitaxial layer is provided. Then, a dielectric layer is formed on the first epitaxial layer. A shielding layer is formed on the dielectric layer. Next, a portion of the shielding and the dielectric layers are removed to form a shielding structure and a dielectric structure on the first epitaxial layer, wherein the shielding structure is stacked on the dielectric structure. A selective epitaxial growth technique is utilized to form a second epitaxial layer surrounding the dielectric and the shielding structures on the exposed surface of the first epitaxial layer and the second epitaxial layer. Afterward, the shielding structure is removed to form a trench on the dielectric structure. A gate oxide layer is further formed on the inner surface of the trench. Lastly, a conducting structure is formed in the trench. | 11-07-2013 |
20130330895 | METHOD OF MANUFACTURING THE TRENCH POWER SEMICONDUCTOR STRUCTURE - A method of manufacturing a trench power semiconductor structure is provided. The method comprising the steps of: providing a base, forming a dielectric pattern layer on the base to define an active region and a terminal region, wherein a portion of the base in the active region and the terminal region is covered by the dielectric pattern layer; selectively forming a first epitaxial layer on the base without being covered by the dielectric pattern layer; removing the dielectric pattern layer in the active region to form a gate trench on the base, and forming a gate dielectric layer on the first epitaxial layer and on the inner surface of the gate trench; forming the gate structure in the gate trench; utilizing the dielectric pattern layer to forming a body on or in the first epitaxial layer; and forming a source on the upper portion of the body. | 12-12-2013 |
20140349456 | TRENCH POWER MOSFET STRUCTURE FABRICATION METHOD - A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss. | 11-27-2014 |
20140361362 | POWER TRANSISTOR HAVING A TOP-SIDE DRAIN AND FORMING METHOD THEREOF - A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced. | 12-11-2014 |