Patent application number | Description | Published |
20120178251 | METHOD OF FORMING METAL PILLAR - The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar. | 07-12-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20130009307 | Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers - A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. | 01-10-2013 |
20130062761 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 03-14-2013 |
20130099371 | SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent. | 04-25-2013 |
20130099385 | Packages and Methods for Forming the Same - A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. | 04-25-2013 |
20130115735 | Apparatus and Methods for Molded Underfills in Flip Chip Packaging - Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed. | 05-09-2013 |
20130122652 | Methods for Performing Reflow in Bonding Processes - A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region. | 05-16-2013 |
20130143364 | METHOD OF PROCESSING SOLDER BUMP BY VACUUM ANNEALING - A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate. | 06-06-2013 |
20130181338 | Package on Package Interconnect Structure - A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer. | 07-18-2013 |
20130214401 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 08-22-2013 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 10-31-2013 |
20130334561 | METHOD FOR BONDING LED WAFER, METHOD FOR MANUFACTURING LED CHIP AND BONDING STRUCTURE - A method for bonding an LED wafer, a method for manufacturing an LED chip, and a bonding structure are provided. The method for bonding an LED wafer includes the following steps. A first metal film is formed on an LED wafer. A second metal film is formed on a substrate. A bonding material layer whose melting point is lower than or equal to about 110° C. is formed on the surface of the first metal film. The LED wafer is placed on the substrate. The bonding material layer is heated at a pre-solid reaction temperature for a pre-solid time to perform a pre-solid reaction. The bonding material layer is heated at a diffusion reaction temperature for a diffusing time to perform a diffusion reaction, wherein the melting points of the first and the second inter-metallic layers after diffusion reaction are higher than about 110° C. | 12-19-2013 |
20140027431 | Warpage Control in the Packaging of Integrated Circuits - A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component. | 01-30-2014 |
20140151878 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 06-05-2014 |
20140159233 | PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate. | 06-12-2014 |
20140193952 | Methods for Metal Bump Die Assembly - Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating. | 07-10-2014 |
20140264856 | Package-on-Package Structures and Methods for Forming the Same - A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. | 09-18-2014 |
20140367867 | Packaging Methods and Packaged Semiconductor Devices - An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux. | 12-18-2014 |
20150044819 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 02-12-2015 |