| Patent application number | Description | Published |
|---|
| 20100252918 | MULTI-DIE PACKAGE WITH IMPROVED HEAT DISSIPATION - The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package. | 10-07-2010 |
| 20100302810 | VOLTAGE CONVERTERS WITH INTEGRATED LOW POWER LEAKER DEVICE AND ASSOCIATED METHODS - Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate. | 12-02-2010 |
| 20110062554 | HIGH VOLTAGE FLOATING WELL IN A SILICON DIE - In one embodiment, a graded n-doped region surrounding a well, and a spiral resistor connected to the well and to a p-doped region surrounding the graded n-doped region. | 03-17-2011 |
| 20110068377 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR WITH SPIRAL FIELD PLATE - In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate. | 03-24-2011 |
| 20110068410 | SILICON DIE FLOORPLAN WITH APPLICATION TO HIGH-VOLTAGE FIELD EFFECT TRANSISTORS - A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation. | 03-24-2011 |
| 20110084333 | POWER DEVICES WITH SUPER JUNCTIONS AND ASSOCIATED METHODS MANUFACTURING - Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material. | 04-14-2011 |
