Patent application number | Description | Published |
20110051100 | METHOD FOR COMPENSATING LIGHT REFLECTION OF PROJECTION FRAME AND PROJECTION APPARATUS - A method for compensating light reflection of a projection frame and a projection apparatus is provided. In the method, a preset frame is projected by the projection apparatus. Next, a spectrum of a light reflected by the projected preset frame is detected and compared with an original spectrum of the preset frame. A light characteristic value of the projected preset frame is then adjusted accordingly, so as to compensate a difference between the detected spectrum of the reflected light and the original spectrum. | 03-03-2011 |
20110304659 | DLP PROJECTOR AND COLOR COMPENSATION METHOD OF BULB OF DLP PROJECTOR - A digital light processing (DLP) projector and a color compensation method of a bulb of the DLP projector are provided. The DLP projector comprises a projecting unit, a sensing unit and a color compensation unit. The projecting unit comprises a bulb, a color wheel and a control module. The control module controls the energy provided for the bulb and the color of the color wheel according to an energy waveform so as to enable the projecting unit to project a plurality of color lights. The sensing unit detects the quality of the color lights projected by the projecting unit. The color compensation unit calculates a difference between the quality detected by the sensing unit and the original quality of each of the color lights, and adjusts the energy waveform accordingly, so as to compensate the difference of each of the color lights. | 12-15-2011 |
20120038743 | Method and Apparatus for Adjusting 3D Video Images - A method for adjusting 3D video images is provided. The method includes the steps of: receiving a 3D video, wherein the 3D video includes a plurality of frames, and each frame includes a plurality of image blocks; obtaining a binocular parallax value between a left eye image and a right eye image which related to each other in the 3D video; calculating displacement of each image block based on the locations of the same image block in the different frames and calculating the image complexity of the 3D video based on the displacements of the image blocks of the frames; converting the 3D video into a 2D video and displaying the 2D video when the image complexity is greater than a predetermined value, and adjusting the definition of depth of each image block in each frame of the 2D video, and displaying the 3D video when the image complexity is lower than the predetermined value, and adjusting the binocular parallax of each image block of each frame of the 3D video according the image complexity of the 3D video. | 02-16-2012 |
20130050203 | DEVICES AND METHODS FOR 3-D IMAGE PROCESSING - A 3-D image processing device for processing a 3-D image data, wherein the 3-D image data has a base frame and a dependent frame, including: an image detection unit, detecting the 3-D image data to obtain the base frame and the dependent frame; an image compensation unit, generating a compensation dependent frame by performing image compensation for the dependent frame based on the base frame; and a display device, displaying a 3-D compensation image data according to the base frame and the compensation dependent frame, wherein the base frame and the dependent frame constitute a visual 3-D image, and the base frame has more image details than the dependent frame. | 02-28-2013 |
Patent application number | Description | Published |
20100250984 | ELECTRONIC DEVICE AND POWER SAVING METHOD THEREOF - The present invention discloses an electronic device and power saving method thereof. In an embodiment, when the electronic device operates in a power-saving mode, which means an area on a screen of the electronic device is not a currently in-focus window-based interface, the area is adjusted to have reduced backlight brightness. Thus, not only the power consumed by the screen is reduced but also user experience can be maintained. In another embodiment, when the electronic device operates in a power-saving mode, display parameters for an image shown in the currently in-focus window-based interface are changed without adversely affecting the power-saving effect, so that the currently in-focus window-based interface has higher display definition than other areas do. | 09-30-2010 |
20110157488 | METHOD AND APPARATUS OF PROJECTOR COLOR ENHANCEMENT BY DYNAMIC LAMP WAVEFORM - A projector of enhanced color visual output and the method of enhancing the color vividness of a projector output, wherein the projector has a program of instructions stored within its memory to perform image data analysis. The image data analysis includes RGB level detection and histogram calculation. The projector dynamically compares these data, using a waveform selection algorithm, to dynamically select an appropriate waveform from a waveform data table stored in the memory. As a result, the projector constantly changes to use a driving waveform for the light source that is appropriate for the content of the projected image. By using a dynamic waveform to vary the light source, the brightness of selected color region is enhanced to improve vividness of color on a projected image. | 06-30-2011 |
20110267360 | STEREOSCOPIC CONTENT AUTO-JUDGING MECHANISM - A method of playing an original 3D content on a 3D enabled monitor, where the 3D enabled monitor does not support the original 3D format type of the original 3D content. The method includes the steps of automatically reading a portion the original 3D content to obtain an identity of the original 3D format type, this portion may or may not be a tag, and reading this portion may include playing multiple frames of the 3D content. The preferred method further includes automatically detecting a monitor and its 3D display format type. If no match is found between the original 3D format type and the display format type, then the method deconstruct the original image content and reconstruct the image content into a 3D format type supported by the 3D display format type. | 11-03-2011 |
Patent application number | Description | Published |
20100220244 | ELETRONIC DEVICE, DISPLAY DEVICE, AND METHOD OF CONTROLLING AUDIO/VIDEO OUTPUT OF AN ELECTRONIC DEVICE - An electronic device, a display device, and a method of controlling audio/video output of the electronic device are disclosed. The electronic device includes a data processing unit, a visual output unit, an audio output unit, and a user operating habit database. The data processing unit executes an application program, the visual output unit outputs an image signal, the audio output unit outputs an audio signal, and the user operating habit database records a corresponding relationship between different program types and operating parameters of the visual output unit or the audio output unit. And, the data processing unit acquires the program type of the application program being run for controlling the operating parameters of the visual output unit or the audio output unit. | 09-02-2010 |
20110304042 | Copper Bump Structures Having Sidewall Protection Layers - A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer. | 12-15-2011 |
20120128457 | Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes - An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports | 05-24-2012 |
20130140690 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 06-06-2013 |
20130334832 | Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes - An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports | 12-19-2013 |
20140061924 | Interconnect Structure and Method - An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line. | 03-06-2014 |
20140077374 | Through Via Structure and Method - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 03-20-2014 |
20140264834 | Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation - Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. | 09-18-2014 |
Patent application number | Description | Published |
20120044168 | TOUCH-CONTROLLED SYSTEM AND METHOD - A touch-controlled system and a touch-controlled method are provided. The touch-controlled system includes a screen, a host, and an electronic pen. The screen is used to display an image with hidden coding. The host is used to drive the screen for displaying. When the electronic touches the screen, the electronic pen captures a part of the image of the screen and sends captured image to the host. At least one hidden information in the captured image. The host analyses and decodes the hidden information, to get a cursor position where the electronic pen touches, and the cursor position is displayed on the screen. | 02-23-2012 |
20120249967 | METHOD FOR ADJUSTING COLOR - A method for adjusting color, suitable for a three dimension (3D) projector, is provided. In the present invention, a plurality of segment ranges of a color wheel is covered one by one, and it is measured a color temperature corresponding to the color wheel after each of the segment ranges is covered. Then, each of the color temperatures is compared with a standard color temperature for choosing one of the color temperatures closest to the standard color temperature. And the segment range corresponding to the color temperatures closest to the standard color temperature is regarded as a correctional covering segment. | 10-04-2012 |
20130324191 | EXTERNAL ELECTRONIC DEVICE AND METHOD FOR WIRELESSLY ACCESSING STORAGE DEVICE - An external electronic device and a method for wirelessly accessing a storage device are provided. The external electronic device includes a peripheral connection interface, a communication unit and an operation interface unit. The peripheral connection interface is connected with a storage device with a corresponding connecting interface. The communication unit is coupled to the peripheral connection interface and configured for communicating with a communication device via a wireless transmission protocol. The operation interface unit is coupled to the peripheral connection interface and the communication unit and has a webpage operation interface, ios application operational interface, and/or android application operation interface related to the storage device. The external electronic device provides the communication device an access service to the storage device through the webpage operation interface, ios application operation interface, and/or android application operation interface. | 12-05-2013 |
20140208019 | CACHING METHOD AND CACHING SYSTEM USING DUAL DISKS - A caching method and a caching system using dual disks, adapted to an electronic apparatus having a first storage unit and a second storage unit, are provided, in which an access speed of the second storage unit is higher than that of the first storage unit. In the method, a data access to the first storage unit is monitored, a data category of the data in an access address of the data access is identified and whether the data category belongs to a cache category is determined. If the data category belongs to the cache category, an access count of the data in the access address being accessed is accumulated and whether the accumulated access count is over a threshold is determined. If the access count is over the threshold, the data in the access address is cached to the second storage unit. | 07-24-2014 |
20150356011 | ELECTRONIC DEVICE AND DATA WRITING METHOD - An electronic device includes a first storage unit, a second storage unit and a control unit. The first storage unit stores the cache of the data. The second storage unit stores the data. The control unit calculates a first ratio of the cache corresponding to the data according to the capacity of the first storage unit. The control unit sends a distribution signal to the processing unit when the control unit reads the data from the second storage unit. The processing unit obtains a first distribution result corresponding to the cache according to the first ratio, and stores the cache to the first storage unit according to the first distribution result. | 12-10-2015 |
Patent application number | Description | Published |
20120155194 | Wordline voltage control within a memory - A memory circuit | 06-21-2012 |
20120170390 | Read stability of a semiconductor memory - A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level. | 07-05-2012 |
20120287733 | Memory circuitry with write boost and write assist - Memory circuitry | 11-15-2012 |
20130308407 | CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DISTURBS IN SEMICONDUCTOR MEMORIES - A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level. | 11-21-2013 |
20140286096 | MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH A MEMORY DEVICE - A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level. | 09-25-2014 |
20160064054 | Double Pumped Memory Techniques - A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal. | 03-03-2016 |
Patent application number | Description | Published |
20130037953 | THROUGH SILICON VIA STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a through silicon via structure includes the following steps. First, a substrate is provided, and a through silicon hole is formed in the substrate. An outer plasma enhanced oxide layer is formed on the surface of the through silicon hole, and then a liner layer is formed on the surface of the outer plasma enhanced oxide layer. An inner plasma enhanced oxide layer is formed on the surface of the liner layer. Finally, a conductor is formed on the surface of the inner plasma enhanced oxide layer to completely fill the through silicon hole. | 02-14-2013 |
20130161796 | THROUGH SILICON VIA AND METHOD OF FORMING THE SAME - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV. | 06-27-2013 |
20130256843 | WAFER SAWING METHOD AND WAFER STRUCTURE BENEFICIAL FOR PERFORMING THE SAME - A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench. | 10-03-2013 |
20130270712 | Through silicon via structure and method of fabricating the same - A through silicon via structure and a method of fabricating the through silicon via structure are disclosed. After an interlayer dielectric is formed, a via hole is then formed to pass through the interlayer dielectric; thereafter, a dielectric liner is formed within the via hole and extends onto the interlayer dielectric; thereafter, the via hole is filled with a conductive material; and a chemical-mechanical polishing process is performed to planarize the conductive material, using the dielectric liner on the interlayer dielectric as a stop layer of the chemical-mechanical polishing process. | 10-17-2013 |
20130299949 | Through Silicon Via and Method of Forming the Same - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface. | 11-14-2013 |
20130299993 | INTERCONNECTION OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present invention provides a method for fabricating an interconnection of a semiconductor device, which includes the following processes. First, an isolation layer is formed on a substrate. Then, at least a first trenches extending along a first direction is formed in the isolation layer. The first trench is then filled up with a first conductive material followed by forming a patterned mask layer on the substrate, wherein the patterned mask exposes parts of the isolation layer and part of the first conductive material. Finally, at least a second trench extending along a second direction is formed in the isolation layer, wherein the at least one second trenches intersects and overlaps portions of the at least one first trenches. | 11-14-2013 |
20130320537 | THROUGH SILICON VIA (TSV) STRUCTURE AND PROCESS THEREOF - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 12-05-2013 |
20130337645 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor. | 12-19-2013 |
20130337650 | METHOD OF MANUFACTURING DUAL DAMASCENE STRUCTURE - A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings. | 12-19-2013 |
20130341799 | Through silicon via structure and method of fabricating the same - A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole. | 12-26-2013 |
20140093814 | METHOD FOR FORMING PHOTOMASKS - A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer. | 04-03-2014 |
20140220482 | METHOD FOR FORMING PATTERNS - A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer. | 08-07-2014 |
20150041961 | Through silicon via structure - A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via. | 02-12-2015 |
20150072272 | Method For Forming Photo-Mask And OPC Method - A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method. | 03-12-2015 |
20150093893 | PROCESS OF FORMING SEED LAYER IN VERTICAL TRENCH/VIA - In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process. | 04-02-2015 |
20150104938 | METHOD FOR FORMING DAMASCENE OPENING AND APPLICATIONS THEREOF - A method for forming a damascene opening, wherein the method comprises steps as follows: Firstly, a semiconductor structure comprising an inter-metal dielectric (IMD), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the IMD. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench. Subsequently, a wet treatment is performed to remove the second hard mask layer and a portion of the first hard mask layer, wherein the plasma-modified portion of the first patterned hard mask layer has a first removing rate substantially less than a second removing rate of the second hard mask layer in the wet treatment. | 04-16-2015 |
20150340280 | THROUGH SILICON VIA (TSV) PROCESS - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 11-26-2015 |