| Patent application number | Description | Published |
|---|
| 20080310223 | Method for programming a multilevel memory - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K | 12-18-2008 |
| 20090021980 | Non-volatile memory and operating method thereof - A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed. | 01-22-2009 |
| 20090021994 | MEMORY AND METHOD FOR PROGRAMMING THE SAME - A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data. | 01-22-2009 |
| 20090231920 | PROGRAMMING METHOD AND MEMORY DEVICE USING THE SAME - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command. | 09-17-2009 |
| 20090303792 | METHOD FOR PROGRAMMING A MULTILEVEL MEMORY - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K | 12-10-2009 |
| 20100002505 | READING METHOD FOR MLC MEMORY AND READING CIRCUIT USING THE SAME - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 01-07-2010 |
| 20100027331 | MEMORY AND READING METHOD THEREOF - A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined value or not. If the threshold voltage of the first half cell is higher than the predetermined value, a second voltage higher than the first voltage is applied to the memory cell to read data stored in the second half cell, otherwise a third voltage lower than the first voltage is applied to the memory cell to read the data stored in the second half cell. | 02-04-2010 |
| 20100039304 | DIGITAL TO ANALOG CONVERTER AND METHOD THEREOF - A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance. | 02-18-2010 |
| 20100302863 | Reading Method for MLC Memory and Reading Circuit Using the Same - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 12-02-2010 |
| 20110055670 | Programming Method and Memory Device Using the Same - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command. | 03-03-2011 |
| 20110058414 | MEMORY WITH MULTIPLE REFERENCE CELLS - A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels. | 03-10-2011 |
| 20110069544 | METHOD AND APPARATUS FOR PROGRAMMING A MULTI-LEVEL MEMORY - A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV | 03-24-2011 |
| 20110085378 | Memory and Operation Method Therefor - In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage. | 04-14-2011 |
| 20110157951 | 3D CHIP SELECTION FOR SHARED INPUT PACKAGES - A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process. | 06-30-2011 |
