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Hsin, TW
Chen-Wei Hsin, Changhua City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090208876 | Long-length fiber Bragg creating sequential UV writing by probing phase mask - A new fiber position monitoring method for sequential FBG UV-writing processes with a reference phase mask as the phase reference is proposed. Also, the new method by probing a reference phase mask can overcome the optical alignment difficulties in using reference fiber as well as provide more signal power for achieving better monitoring accuracy. Moreover, the present invention provides a method for sequentially joining a plurality of grating sections into a fiber grating longer than a phase mask. | 08-20-2009 |
Chia-Fen Hsin, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100225230 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a light emitting diode package structure is disclosed. First, a carrier and an LED chip are provided, wherein the LED chip is disposed on the carrier. Next, a first molding compound is provided on the LED chip, wherein the first molding compound is mixed up with a fluorescent material. Then, a first baking process to make the first molding compound in semi-cured state is performed. After that, a second molding compound is provided on the first molding compound. | 09-09-2010 |
Chia-Fen Hsin, New Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110227118 | Light Emitting Diode Package Structure and Manufacturing Method Thereof - A light emitting diode package structure is disclosed. The LED package structure includes a carrier, an LED chip, a first molding compound and a second molding compound. The LED chip is disposed on the carrier. The first molding compound overlays the LED chip, wherein the first molding compound is mixed up with a fluorescent material. The second molding compound overlays the first molding compound. | 09-22-2011 |
Chien-Jung Hsin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080222595 | METHOD OF ENGINEERING CHANGE TO SEMICONDUCTOR CIRCUIT EXECUTABLE IN COMPUTER SYSTEM - A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit. | 09-11-2008 |
Ching-Ya Hsin, New Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120065942 | METHOD OF AN ALL-SPEED PROPELER - A design method of an all-speed propeller includes five steps; a first step (A) of creating a basic shape of an all-speed propeller, a second step (B) of optimization of circulation distribution, a third step (C) of adjusting the shape of the all-speed propeller, a fourth step (D) of analysis of thrust and torsion and fifth step (E) of finishing the design of the all-speed propeller. With parameters of a design request repeatedly processed by a lifting line program, a lifting surface program and a boundary element program in the steps mentioned previously, the all-speed propeller can lower cavitation effect caused by different speeds on the capacity of the propeller, so as to enable efficiency kept rather high without sharply lowering while navigating in diverse speeds. | 03-15-2012 |
Ching-Yeh Hsin, Tamshui TW
| Patent application number | Description | Published |
|---|---|---|
| 20110059663 | ADVANCED FOIL DESIGN METHOD AND STRUCTURE FOR MULTI SPEEDS - Advanced foil design method and structure for multi speeds mainly adds a constraint according to a needed pressure distribution of the advanced foil after building an advanced foil environment. Thence, a step of optimization could be applied for analyzing the advanced foil by flow characteristics to achieve a shaped profile, so that a weight calculation weighted calculation would be further operated base on a proportion of the advanced coil applied to multi speeds. Accordingly, a preferable profile of the advanced foil and the environment parameter combination can be obtained to enhance a higher operative efficiency with the preferred benefit of the Supercavitating propeller while applied to a higher speed and with the profit of a stable competence while applied to a lower speed. | 03-10-2011 |
Chiung-Wen Hsin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120083138 | Electronic Device - An electronic device is provided. The electronic device includes a substrate and a joint. The substrate includes a first surface and a second surface, wherein a substrate signal contact, two ground contacts and two positioning openings are formed on the substrate, and the positioning openings are respectively formed on the ground contact and pass through the substrate. The joint includes a connection port, a joint signal contact and two ground structure, wherein the connection port is electrically connected to the joint signal contact, the joint signal contact is connected to the substrate signal contact, and the joint signal contact is located between the two ground structures, and the ground structures are respectively inserted into the positioning openings to be electrically connected to the ground contacts. | 04-05-2012 |
Chu-Han Hsin, Keelung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100300369 | Covering structure for exterior of aquarium - The present invention provides a covering structure for exterior of aquarium, which includes a peripheral covering layer configured with a plurality of slide grooves that provide effectiveness of tracks and enable a tight fit to the corners of an aquarium. The covering structure thus provides a sliding means to interplay with the aquarium, moreover, extending the peripheral covering layer provides additional holding space, and increasing the plurality of slide grooves enables further segmentation, thereby augmenting the holding capacity of the covering layer and enabling variability in outward appearance to transform the aquarium into a craftwork similar to a building. Furthermore, the covering structure is joined to the corners of the aquarium using the slide grooves and a mounting method, which saves on time and provides a quick method to change the outward appearance of the aquarium, presenting a design of economic benefit and improving appreciative value of the aquarium. | 12-02-2010 |
Chung-Hsien Hsin, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090045476 | IMAGE SENSOR PACKAGE AND METHOD FOR FORMING THE SAME - An image sensor package is provided including a substrate; a sensor chip; a plurality of bond wires for connecting the sensor chip to the substrate at predetermined locations; a sensor housing on the substrate for substantially encompassing the sensor chip, the sensor housing having a through-hole cavity defining an optical glass (IR filter) seat, the sensor housing defining an upper surface and an edge surface thereof; an optical glass (IR filter) on the optical glass (IR filter) seat; an encapsulation material for substantially encapsulating the upper surface and edge surface of the sensor housing, a corresponding surface of the substrate adjacent the edge surface of the sensor housing, and the side edge of the optical glass (IR filter); wherein the sensor housing is provided with a gas-exit allowing possible high temperature gas to exit; the encapsulation material forms an upper surface which is substantially aligned with a top surface of the optical glass (IR filter); the encapsulation material forms an upper surface which is lower than a top surface of the optical glass (IR filter); the sensor housing defines a profile shape, the profile shape has at least a step-wise configuration for facilitating and accommodating flowing of the encapsulation material; the sensor housing has a bottom surface adhered to the substrate by an adhesive; and a slot is provided on the bottom surface of the sensor housing for accommodating the adhesive. | 02-19-2009 |
| 20090283809 | Image sensor structure and integrated lens module thereof - An image sensor structure and an integrated lens module thereof are provided. In the image sensor structure with the integrated lens module, the image sensor structure comprises a chip and a lens module. The chip has light-sensing elements, first conducting pads, and a conducting channel. The light-sensing elements are electrically connected to the first conducting pads and the first conducting pads are electrically connected to one end of the conducting channel passing through the chip. The lens module comprises a holder and at least one lens. The holder has a through hole and the lens is embedded in the through hole and integrated with the holder. By using the integrated lens and holder, a manufacturing process of the image sensor structure is simplified and a manufacturing cost of the image sensor structure is reduced. | 11-19-2009 |
Chung-Hsien Hsin, Chu-Pei TW
| Patent application number | Description | Published |
|---|---|---|
| 20110024862 | IMAGE SENSOR PACKAGE STRUCTURE WITH LARGE AIR CAVITY - The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized. | 02-03-2011 |
| 20110241146 | MANUFACTURING METHOD AND STRUCTURE OF A WAFER LEVEL IMAGE SENSOR MODULE WITH PACKAGE STRUCTURE - The present invention discloses a manufacturing method and structure of a wafer level image sensor module with package structure. The structure of the wafer level image sensor module with package structure includes a semi-finished product, a plurality of solder balls, and an encapsulant. The semi-finished product includes an image sensing chip and a wafer level lens assembly. The encapsulant is disposed on lateral sides of the image sensing chip and the wafer level lens assembly. Also, the manufacturing method includes the steps of: providing a silicon wafer, dicing the silicon wafer, providing a lens assembly wafer, fabricating a plurality of semi-finished products, performing a packaging process, mounting the solder balls, and cutting the encapsulant. Accordingly, the encapsulant encapsulates each of the semi-finished products by being disposed on the lateral sides thereof. | 10-06-2011 |
| 20110241147 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method of the same. The manufacturing method includes the following steps: providing a silicon wafer, dicing the silicon wafer, providing a plurality of transparent lids, fabricating a plurality of semi-finished products, performing a packaging process, mounting solder balls, and cutting an encapsulant between the semi-finished products. The manufacturing method of the invention has the advantage of being straightforward, uncomplicated, and cost-saving. Thus, the wafer level image sensor package structure is lightweight, thin, and compact. To prevent the image sensor chip from cracking on impact during handling, the encapsulant will be arranged on the lateral sides of the semi-finished products during the packaging process. | 10-06-2011 |
Chung-Hsien Hsin, Chu-Pei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110024610 | IMAGE SENSOR PACKAGE STRUCTURE - The present invention discloses an image sensor package structure. The image sensor package structure includes a substrate, a chip, a transparent lid, a first casing and a package material. The transparent lid covers a sensitization area of the chip and it also adheres to the chip which is deposed on the substrate. The first casing, which adheres to the transparent lid, forms an opening so that light can pass through the opening and the transparent lid to enter into the sensitization area. The package material covers around the chip and the transparent lid and fills between the substrate and the first casing. Because of the arrangement of adhesive layers placed between the first casing and the transparent lid and between the transparent lid and the chip, the blockage area from moisture is elongated. Therefore, the reliability of the image sensor package structure can be enhanced. | 02-03-2011 |
| 20110024861 | MANUFACTURING METHOD FOR MOLDING IMAGE SENSOR PACKAGE STRUCTURE AND IMAGE SENSOR PACKAGE STRUCTURE THEREOF - A manufacturing method for molding an image sensor package structure and the image sensor package structure thereof are disclosed. The manufacturing method includes following steps of providing a half-finished image sensor for packaging, arranging a dam on the peripheral of a transparent lid of the half-finished image sensor, positioning the half-finished image sensor within a mold, and injecting a mold compound into the mold cavity of the mold. The dam is arranged on the top surface of the transparent lid and the inner surface of the mold can exactly contact with the top surface of dam so that the mold compound injected into the mold cavity is prevented from overflowing to the transparent lid by the dam. Furthermore, the arrangement of the dam and the mold compound can increase packaged areas and extend blockage to invasive moisture so as to enhance the reliability of the image sensor package structure. | 02-03-2011 |
Chung-Hsien Hsin, Hsin-Chu Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20110156187 | IMAGE SENSOR PACKAGING STRUCTURE WITH PREDETERMINED FOCAL LENGTH - An image sensor packaging structure with a predetermined focal length is provided. The image sensor packaging structure includes a substrate, a chip, an optical assembly, and an encapsulation compound. The chip has a sensitization area and is coupled to the substrate. Conductive contacts on the substrate are electrically connected with conductive contacts around the sensitization area. The optical assembly has the predetermined focal length and is disposed above the chip so as to form an air cavity between the optical assembly and the sensitization area of the chip. The encapsulation compound is formed on the substrate to surround the chip and the optical assembly. With the above stated structure, not only can the focus adjusting procedure be dispensed with, but also the image sensor packaging structure can be manufactured by a molding or dispensing process. | 06-30-2011 |
| 20110156188 | IMAGE SENSOR PACKAGING STRUCTURE WITH LOW TRANSMITTANCE ENCAPSULANT - An image sensor packaging structure with a low transmittance encapsulant is provided. The image sensor packaging structure includes a substrate, a chip, a transparent lid, and the low transmittance encapsulant. The chip is combined with the substrate. The transparent lid is adhered to the chip and cover above a sensitization area of the chip to form an air cavity. The low transmittance encapsulant is formed on the substrate and encapsulates the chip and the transparent lid so as to accomplish the package of the image sensor packaging structure. Due to the feature of prohibiting from light passing through the low transmittance encapsulant, the arrangement of the low transmittance encapsulant can avoid the light from outside interfere the image sensing effect of the image sensor. Therefore, the quality of the image sensing can be ensured. | 06-30-2011 |
| 20110279815 | MANUFACTURING METHOD AND STRUCTURE FOR WAFER LEVEL IMAGE SENSOR MODULE WITH FIXED FOCAL LENGTH - This present invention discloses a manufacturing method and structure for a wafer level image sensor module with fixed focal length. The method includes the following steps. First, a silicon wafer comprising several image sensor chips having a photosensitive area and a lens module array wafer comprising several wafer level lens modules with fixed focal length are provided. Next, the image sensor chips and the wafer level lens modules are sorted in grades according to the different quality grades. According to the sorting results, each of the wafer level lens modules is assigned to be situated above the image sensor chip that has the same grade. At the same time, each of the wafer level lens modules is directed to face the photosensitive area of each image sensor chip. Finally, in the packaging process, the wafer level lens module is surrounded by an encapsulation material. | 11-17-2011 |
| 20110291215 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced. | 12-01-2011 |
| 20120068288 | MANUFACTURING METHOD OF MOLDED IMAGE SENSOR PACKAGING STRUCTURE WITH PREDETERMINED FOCAL LENGTH AND THE STRUCTURE USING THE SAME - A manufacturing method of a molded image sensor packaging structure with a predetermined focal length and the structure using the same are disclosed. The manufacturing method includes: providing a substrate; providing a sensor chip disposed on the substrate; providing a lens module set over the sensing area of the chip to form a semi-finished component; providing a mold that has an upper mold member with a buffer layer; disposing the semi-finished component into the mold to form a mold cavity therebetween; injecting a molding compound into the mold cavity; and after transfer molding the molding compound, opening the mold and performing a post mold cure process to cure the molding compound. The buffer layer can fill the air gap between the upper surface of the lens module and the upper mold member, thereby preventing the upper surface of the lens module from being polluted by the molding compound. | 03-22-2012 |
Ding-Yu Hsin, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110125942 | SIGNAL SWING TRIMMING APPARATUS AND METHOD THEREOF - A signal swing trimming apparatus calibrates a swing level of an output signal generated from a transmitting device to a receiving device including: a comparing device coupled to the output signal for comparing the swing level of the output signal with a target swing level and generating a comparison output signal, and an adjusting device coupled to the comparing device and the transmitting device for controlling the transmitting device to adjust the swing level of the output signal according to the comparison output signal, wherein the signal swing trimming apparatus is configured to calibrate the swing level of the output signal during a hand-shake process between the transmitting device and the receiving device. | 05-26-2011 |
Don-Chen Hsin, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090015296 | DIGITAL FREQUENCY SYNTHESIZER AND METHOD THEREOF - A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved. | 01-15-2009 |
| 20090021499 | DISPLAY DRIVING APPARATUS AND METHOD THEREOF - A display driving apparatus and a method thereof are provided. The apparatus includes a memory unit, a compression and decompression unit, a data selection unit, and a display accelerating unit. The memory unit is coupled to the compression and decompression unit and stores only a compressed frame to save memory space in the apparatus. The data selection unit determines whether an error is caused to a frame through data compression and decompression. When the error is greater than a predetermined value, the display accelerating unit turns off an overdriving process upon the pixels to avoid image distortion. The data selection unit also determines whether the frames are static or dynamic in order to determine whether to turn on the overdriving process. | 01-22-2009 |
Huang Chih Hsin, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080282474 | Structure improvement of the pillow - The present invention relates to an “structure improvement of the pillow”, which comprises a central main pillow and two lateral sub-pillows, wherein, said central main pillow is trapezoid in dimension with height of pillow top and central length such that the height of pillow top approximately equals the distance between the outer hind skull surface to the outer surface of the normal arched cervical vertebra when people lies on one's back while the height of central length approximately equals the distance between the outer side surface of two ears of human head with slight clearance for tolerance; said lateral sub-pillow is trapezoid in dimension with height of pillow top and the height of pillow top approximately equals the distance between the outer side skull surface to the outer side surface of the shoulder when people lies on one's side; The characterized is that a pair of symmetrical skew-angled arrangement for said central main pillow and each of said two lateral sub-pillows is formed in disposal so that the user head can be exactly placed on and closely supported by one of the two lateral sub-pillows completely when the user lies on one's side sleeping posture; Besides, a sunken dent space is created on the central top of the lateral sub-pillow so that the user ear will be not pressed without uncomfortable feeling. | 11-20-2008 |
I-Chien Hsin, Banciao City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080264124 | Lock core assembly with multiple burglarproof effects - A lock core assembly has a lock shell, a lock core mounted rotatably in the lock shell, multiple pin assemblies and an arrestor. Multiple mounting chambers are formed between the lock core and the lock shell. The pin assemblies are mounted respectively in the mounting chambers and each have an upper pin situated at an interface between the lock core and the lock shell to prevent a rotation of the lock core and a lower pin with an annular groove. The lock shell has a retaining cavity formed inside. The lock core has a mounting recess communicating with the mounting chambers and aligning with the retaining cavity. The arrestor is mounted slidably in the mounting recess. Without inserting a right key into the lock core, the arrestor is held in the retaining cavity to prevent the lock core from rotating to provide an improved burglarproof effect. | 10-30-2008 |
| 20080264125 | Lock assembly with an improved burglarproof lock core - A lock assembly with an improved burglarproof lock core has a casing, a lock core and multiple outer chambers. The casing is mounted in a lock device and has a core hole and multiple outer chambers. The lock core is mounted in the core hole and has multiple inner chambers and a keyhole. The inner chambers correspond to the outer chambers in the casing. Each locking pin assembly is mounted slidably in the corresponding outer and inner chambers and has an inner and outer locking. The inner locking pins are flush with the inner chamber when the lock device is unlocked, and at least one inner locking pin is magnetic. The outer locking pin corresponding to the magnetic locking pin is held to ensure that the lock assembly won't be unlocked when someone attempts to tap the locking pin assemblies to pick the lock device. | 10-30-2008 |
| 20080302150 | LOCK CORE ASSEMBLY - A lock core assembly has a lock shell, a lock core, multiple pin assemblies and at least one anti-knock pin assembly. Each pin assembly is mounted in a mounting chamber formed radially in the lock shell and through the lock core. Each anti-knock pin assembly has an upper pin and a major spring abutting each other and is mounted in a corresponding characteristic chamber assembly with a core chamber and at least one limiting recess communicating with each other. When a burglar turns the lock core by using a lock pick to vibrate or knock the lock core, the major spring presses the upper pin to engage in the limiting recess to limit the lock core and provide a reliable and reusable burglarproof lock that need not be replaced after an attempted malicious opening. | 12-11-2008 |
| 20090178451 | Lock core assembly - A lock core assembly has a lock shell, a lock core and a pin segment. The lock shell has a core mount, multiple upper pin chambers, a lid and at least one retaining flange. The lock core is mounted rotatably in the core mount and has a keyhole and multiple lower pin chambers. The lower pin chambers are formed radially through an outer surface of the lock core, communicate with the keyhole, align longitudinally, correspond to and communicate with the upper pin chambers. The pin segment is mounted between the lock shell and the lock core and has multiple abutting pin assemblies and at least one suspended pin assembly. When knocked, a suspended upper pin of the at least one suspended pin assembly prevents the pin aligning and the lock core from rotating, the lock core assembly provides a preferred burglarproofing effect. | 07-16-2009 |
I-Chien Hsin, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20110041576 | LOCK CORE ASSEMBLY - A lock core assembly has a lock shell, a lock core and a pin segment. The lock shell has multiple upper pin chambers and a lid. The lock core is mounted rotatably in the lock shell and has multiple lower pin chambers. The lower pin chambers are formed radially through an outer surface of the lock core and respectively align and communicate with the upper pin chambers. The pin segment is mounted between the lock shell and the lock core and has multiple pin assemblies including at least one suspended pin assembly. Each suspended pin assembly has a suspending spring and a suspending block. The suspending spring is connected to a lower pin. The suspending block is mounted on and supported by the suspending spring and abuts with a returning spring. | 02-24-2011 |
Kuo-Ting Hsin, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100272139 | DRIVING CIRCUIT FOR DRIVING LASER DIODE AND METHOD FOR CONTROLLING LASER POWERS OF LASER DIODE - The invention provides a driving circuit for driving a laser diode of a pickup head. In one embodiment, the driving circuit comprises an automatic power control (APC) module, a clamp value determination unit, and a clamp circuit. The automatic power control module generates at least one power control signal. The clamp value determination unit dynamically determines at least one clamp value corresponding to the power control signal when the pickup head accesses an optical storage medium. The clamp circuit clamps the power control signal according to the clamp value to obtain a clamped power control signal. A driving signal for driving the laser diode can then be generated according to at least the clamped power control signal. | 10-28-2010 |
Kuo-Ting Hsin, Hsin-Chu Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080253240 | METHOD AND SYSTEM FOR CALIBRATING RECORDING TRACK OFFSET OF OPTICAL STORAGE DEVICE - A method for calibrating a recording track offset of an optical storage device accessing an optical storage medium of a land and groove recording/reproduction type includes: setting at least one control parameter of a track offset control loop of the optical storage device to drive the track offset control loop to enter an first state; and recording data onto the optical storage medium with the track offset control loop being enabled to derive the latest value of the recording track offset, where the track offset control loop is utilized for controlling the recording track offset. The method further includes setting the control parameter to drive the track offset control loop to enter a second state, where a loop response of the track offset control loop in the first state is different from that in the second state. | 10-16-2008 |
| 20080253248 | SYSTEM AND METHOD FOR CALIBRATING RECORDING TRACK OFFSET OF OPTICAL STORAGE DEVICE - A system and method for calibrating a recording track offset of an optical storage device accessing an optical storage medium of land/groove type. The system includes: a tracking servo loop arranged to control tracking operations of an optical head of the optical storage device; a track offset control loop arranged to control the recording track offset for the tracking servo loop; a controller arranged to enable a latest value of the recording track offset to be a readout value for utilization in a recording process performed later; and a comparator arranged to compare a recording length with a threshold value and generate a flag to represent whether the recording length is a long recording length, wherein the latest value is derived from the track offset control loop. | 10-16-2008 |
| 20090141598 | Apparatus for Adjusting Focus Offset and Method Thereof - The present invention provides an apparatus of an optical disc drive for adjusting a focus error signal. The apparatus includes a focus offset determining unit and an adjusting module. The focus offset determining unit is utilized for determining a target focus offset corresponding to a target condition, and the adjusting module is coupled to the focus offset determining unit and utilized for receiving the focus error signal and adjusting the focus error signal with the target focus offset to generate an adjusted focus error signal. | 06-04-2009 |
Kuo-Ting Hsin, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110158065 | Optical Disk Drive and Method for Performing Layer Jumps - The invention provides a method for performing a layer jump of a disk. First, a tracking error generation method is determined according to a layer type of a target layer when the layer jump is performed. A tracking error signal is then generated according to the tracking error generation method. | 06-30-2011 |
| 20110158070 | Optical Disk Drive and Method for Determining Type of a Blu-Ray Disk - The invention provides a method for determining the layer type of a blu-ray disk. First, a laser beam is focused on a target layer of the blu-ray disk. Reflection of the laser beam from the target layer is the detected to obtain a reflection signal. The reflection signal is then processed to generate a first tracking error signal and a second tracking error signal. Magnitudes of the first tracking error signal and the second tracking error signal are then measured. The magnitude of the second tracking error signal is then subtracted from the magnitude of the first tracking error signal to obtain a difference value. Finally, the layer type of the target layer is determined by comparing the difference value with the first predetermined threshold. | 06-30-2011 |
Lung-Pin Hsin, Tai Chung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090323013 | MODULIZED DISPLAY COMPONENT AND MANUFACTURING METHOD THEREOF - A modulized display component and a manufacturing method for the same are disclosed in this invention. The display component of this invention is designed according to a modulization concept so that it can be attached to any driving circuit layer. Further, various manufacturing techniques can be used to form the alignment layers and protective layers in order to fabricate a trans-reflective, reflective, or transmissive color displaying component. | 12-31-2009 |
Tung-Cheng Hsin, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110012689 | Impedance Adjustment Circuit for Adjusting Terminal Resistance and Related Method - An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal. | 01-20-2011 |
| 20110050681 | LOW VOLTAGE DIFFERENTIAL SIGNAL OUTPUT STAGE - A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal. | 03-03-2011 |
Yi-Chih Hsin, Kao Hsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100049898 | MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF - The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank. | 02-25-2010 |
Yite Hsin, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090073056 | Stylus arranged with antenna and portable wireless communication device having the same - A portable wireless communication device has a stylus and a main body. The stylus includes a pen tube and an antenna. The antenna is containable in the pen tube and separable from the pen tube. A portable wireless communication device includes a circuit board arranged in the main body, a containing groove and an antenna groove formed in the main body. The circuit board has a wireless communication unit. The containing groove is configured for containing the stylus. The antenna groove is configured for containing the antenna, and the antenna connects electrically to the wireless communication unit of the circuit board when the antenna is contained in the antenna groove. | 03-19-2009 |
Yue-Ming Hsin, Tainan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080197422 | Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 08-21-2008 |
| 20080299714 | Planar Combined Structure of a Bipolar Junction Transistor and N-type/P-type Metal Semiconductor Field-Effect Transistors and Method for Forming the Same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 12-04-2008 |
| 20090001489 | SILICON PHOTODETECTOR AND METHOD FOR FORMING THE SAME - A structure of a silicon photodetector and a method for forming the same by using the conventional CMOS semiconductor manufacturing process and micro-electromechanical system manufacturing process, in which the micro-electromechanical system manufacturing process (lateral etching process) is applied for elimination of effect and interference caused by a substrate of the silicon photodetector after optical absorption thereof, thereby greatly improving the response speed of the silicon photodetector. This can be done only by applying the lateral etching process onto a portion of the substrate of the silicon photodetector after the semiconductor manufacturing process is finished, through which slow diffusion carriers produced from the optical absorption of the substrate can be effectively reduced and the response speed is thus enhanced. | 01-01-2009 |
| 20110059533 | FLUORESCENCE DETECTION SYSTEM, METHOD, AND DEVICE FOR MEASURING BIOMOLECULES - A fluorescence detection system for measuring biomolecules is disclosed, which includes a fluorescence detection device, a light source, a sample-loading unit, and an analysis-reading device. The fluorescence detection device has a substrate and plural phototransistors arranged on the substrate, and each phototransistor contains an emitter, a collector locating on the substrate, and a base between the emitter and the collector. The base-collector diode junction functions as an absorber to convert fluorescence to photocurrent. The light source serves to excite a fluorescent dye contained in a biomolecule sample. The sample-loading unit is used to load or transport the excited biomolecule sample onto a sensing zone of the fluorescence detection device. The analysis-reading device is to measure photocurrent output from the fluorescence detection device under a bias. Hence, the biomolecule content can be easily determined by the fluorescence detection system. | 03-10-2011 |
| 20110079708 | SILICON PHOTODETECTION MODULE - A silicon photo-detection module is disclosed, in which a silicon photodiode detection unit and a parasitical vertical bipolar junction transistor amplification unit can be simultaneously formed by a CMOS process. The silicon photo-detection module has a silicon substrate, a silicon photodiode detection unit comprising a positive portion and a negative portion, and a parasitical vertical bipolar junction transistor amplification unit comprising a collector, a base, and an emitter. The silicon photodiode detection unit and the parasitical vertical bipolar junction transistor amplification unit are formed on the silicon substrate by a CMOS process. Besides, the positive and negative portions of the silicon photodiode detection unit are electrically connected respectively with the base and the collector of the parasitical vertical bipolar junction transistor amplification unit. | 04-07-2011 |
Yu-Jen Hsin, Tainan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090007397 | GASKET FOR FASTENING THE AUTOMOTIVE SAFETY BELT - The present invention is related to a gasket for fastening the automotive safety belt. A colloidal material is applied to form a one-piece body comprising a fixing part, a flexible part and a plug part. The plug part of the gasket is inlet into the hole of the suspension sheet of the safety belt for fastening the safety belt so as to avoid the safety belt rolling automatically to bind the human body so close that the chest are oppressed uncomfortably. In addition, the gasket mounted on the outer surface of the buckle of safety belt is made of colloidal materials. Even the gasket is touched with human body in use, to adjust and to fasten the safety belt will not result in the human body being hurt from impact. It is much safer for utility. | 01-08-2009 |
Yu-Lin Hsin, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120003479 | SURFACE MODIFICATION OF NANO-DIAMONDS AND MANUFACTURING METHOD THEREOF - The invention is related to a technique that grafts polymer onto a surface of nano-diamonds, and the invention further provides applications relating to modification and dispersion of the nano-diamonds. The features of the technique are single step, one pot, low cost, and high yield, and therefore the technique has high potential for commercialization. The invention also provides a method for graphitizing monocrystalline nano-diamonds and polycrystalline nano-diamonds. Accordingly, the technique of modifying and polymer grafting can be used not only on ultra disperse diamonds but also on monocrystalline nano-diamonds with graphitized surfaces and polycrystalline nano-diamonds with graphitized surfaces. | 01-05-2012 |