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Hsieh, Hsinchu City
Betty Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110062526 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer. | 03-17-2011 |
Chang-Huain Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100177190 | MICROSCOPY SYSTEM WITH REVOLVABLE STAGE - A microscopy system includes an image focusing module, a stage for supporting a sample, image collection unit for collecting sliced images of the sample acquired by the image focusing module, and an image fusion unit for fusing sliced images of the sample acquired from different observation angles. The stage supports the sample and is configured to be revolvable around a rotational axis which is substantially perpendicular to an extending direction from the sample to the image focusing module so that enabling the image focusing module to acquire sliced images of the sample from different observation angles. The image fusion unit is used for remapping the sliced images acquired from different observation angles into a reference coordinate system, converting anisotropic voxels resolution of the sliced images to isotropic resolution, and fusing the sliced images into a final image. | 07-15-2010 |
Chao-Hsiang Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120060926 | POLYMERIZABLE FULLERENE DERIVATIVE AND THEIR USE IN ORGANIC PHOTOVOLTAIC CELLS - The present invention discloses an inverted organic photovoltaic cell comprising a polymerizable fullerene interlayer adapted to enhance the device performance and lifetime. The polymerizable fullerene derivative comprises a fullerene core, a bridging functional group and a polymerizable functional group. The fullerene core can be either C | 03-15-2012 |
Chien Te Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100267276 | Strap with transmission line functionality - A strap with transmission line functionality includes a strap body, a first connecting end and a second connecting end. The strap body has at least one signal line wrapped therein. The first connecting end is disposed at one end of the strap body and the second connecting end is disposed at an opposite end of the strap body so that signals can be transmitted between the first connecting end and the second connecting end via the signal line disposed in the strap body. The first connecting end is directly fixed to and electrically connected with an electronic product, and a signal connector is also disposed at the second connecting end to connect with an external device. The strap body is substantially looped into a circular form so as to be used as a wrist strap or a neck strap of the electronic product. | 10-21-2010 |
Chih-Wel Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100285991 | COMBINATORY ANALYTICAL STRIP - A combinatory analytical strip including a substrate is disclosed. A first channel for a biochemical assay and a second channel for an immunological assay are provided concavely on an upper surface of the substrate. The results of both assays are detected by a sensor. Each channel includes a first area for receiving a fluid sample, a second area for delivering the fluid sample and a third area where the fluid sample reacts. These three areas are connected successively. A nitrocellulose layer having a hollow-matrix conformation is formed at a bottom of each of the second and third areas of both channels. Each of the nitrocellulose layers of the second areas comprises an average thickness that is not greater than that of each the nitrocellulose layers of the third areas. A reaction material is formed in the hollow-matrix conformation. The third areas of the first and second channels are both located on a line conforming a relative motion path of the sensor and the combinatory analytical strip. | 11-11-2010 |
Chin-Kun Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110007521 | BACKLIGHT MODULE WITH A HEAT CONDUCTIVE BLOCK - A backlight module includes a bezel having at least one edge, a circuit board, one or more light emitting diodes connected to the circuit board for emitting light. Each light emitting diode has a light axis which is neither parallel nor vertical to the edge of the bezel. The backlight module utilizes a heat conductive block disposed between the bezel and the light emitting diode for transferring heat generated by the light emitting diode to the bezel. | 01-13-2011 |
| 20120113675 | LAMP DEVICE WITH COLOR-CHANGEABLE FILTER - A lamp device includes a supporting frame, a light emitting diode (LED) array source, a light filter, two end caps and two couples of electrodes. The LED array source is disposed on the supporting frame. The light filter is arc-shaped and combined with the supporting frame as a tubular structure, wherein the arc surface of the light filter is a light emitting surface of the LED array source. The light filter is used for absorbing a ray in a specific wavelength range of the emitting light of the LED array source. The two end caps are disposed at two ends of the tubular structure respectively. The two couples of electrodes are disposed at two ends of the tubular structure and mounted on the two end caps respectively for electrically connecting to the LED array source. | 05-10-2012 |
Chris Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090294886 | METHOD OF MAKING WAFER STRUCTURE FOR BACKSIDE ILLUMINATED COLOR IMAGE SENSOR - An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic. | 12-03-2009 |
Chung-An Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090278607 | Power Supply Device For Driving An Amplifier - A power supply device for driving first and second amplifiers includes a first power generator, a second power generator, a charge pump and a control unit. The first power generator provides a first voltage for first power reception ends of the first and second amplifiers. The second power generator provides a second voltage. The charge pump is coupled between the second power generator and a second power reception end of the first amplifier and between the second power generator and a second power reception end of the second amplifier, and is used for generating a third voltage for the first and second amplifiers according to the second voltage. The control unit is coupled to the second power generator and is used for controlling the second power generator, so as to adjust the second voltage to make the third voltage equal to a multiple of the first voltage. | 11-12-2009 |
| 20090278608 | Power Supply Device for Driving an Amplifier - A power supply device for driving an amplifier includes a power generator for providing a first voltage for a first power reception end of the amplifier, a power conversion unit coupled to the power generator, for converting the first voltage into a second voltage, a charge pump coupled between the power conversion unit and a second power reception end of the amplifier, for generating a third voltage for the amplifier according to the second voltage, and a control unit coupled to the power conversion unit, for controlling the power conversion unit, so as to adjust the second voltage to make the third voltage equal to a specific multiple of the first voltage. | 11-12-2009 |
| 20110304396 | POWER AMPLIFIER AND PROCESSING DEVICE UTILIZING THE SAME - A processing device including a control unit and a power amplifier is disclosed. The control unit generates a plurality of control signals according to an input signal. The power amplifier includes a plurality of switches. The control signals control the switches to turn on or off such that a short through current does not occur in the power amplifier. | 12-15-2011 |
Chung-Hsuan Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090302825 | CURRENT SOURCE - A current source includes a node, a biasing circuit, a loading circuit and a current mirror. The node has a specified voltage. The biasing circuit biases the specified voltage to be a first reference voltage. The loading circuit provides an equivalent resistor across the node and a second reference voltage to generate a reference current. The loading circuit includes a resistor and a metal oxide semiconductor field effect transistor (MOSFET). The resistor has a first temperature coefficient. The transistor operating in a linear region is controlled by a control voltage to turn on and to form a transistor resistor coupled with the resistor in series. The transistor resistor has a second temperature coefficient, wherein a temperature coefficient of the equivalent resistor is relevant to the first and second temperature coefficients. The current mirror receives the reference current and provides a mirrored current of the reference current as the output current. | 12-10-2009 |
Chun-Hsing Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080198267 | Interlaced image processing method and apparatus - In an interlaced image processing method for processing fields generated by interlacing and including a plurality of rows of scan signals, the method includes: performing horizontal line detection on a current field so as to determine which of the rows of the scan signals is a horizontal line; according to the horizontal line detection result of the current field and a horizontal line detection result of a previous field, adjusting position of the horizontal line in the current field so as to approach position of a corresponding horizontal line in the previous field; and according to the result of position adjustment, re-sampling the current field. An interlaced image processing apparatus for implementing the method is also disclosed. | 08-21-2008 |
| 20100085486 | IMAGE PROCESSING APPARATUS AND METHOD - An image processing apparatus includes a pixel difference calculator, a summing unit, a determining unit, and an output unit. The pixel difference calculator receives a present image having first pixels and a previous image having second pixels, calculates pixel differences between corresponding first and second pixels, and outputs positive and negative pixel difference values. The summing unit obtains a first output value by adding up those of the positive pixel difference values and a second output value by adding up those of the negative pixel difference values. The determining unit determines a noise level of the present image from the first and second output values, and outputs a blended value. The output unit adds together weights of pixels at the same positions of the present and previous images according to the blended value to generate an output image. An image processing method is also disclosed. | 04-08-2010 |
| 20100092044 | Image Processing Apparatus and Method - An image processing apparatus includes: a pixel difference calculator for calculating a difference value between each first pixel of a previous image and a second pixel of a present image and at a position corresponding to said each first pixel, and outputting a plurality of pixel differences; a counter counting a number of positive pixel differences and a number of negative pixel differences in the pixel differences of a sampling window; a motion level determining unit calculating a motion level of a pixel in the sampling window according to the numbers of the positive and negative pixel differences; a blending value determining unit determining a blending value according to the motion level; and an output unit adding together weights of the present and previous images according to the blending value to generate and output an output image. An image processing method is also disclosed. | 04-15-2010 |
| 20100104202 | IMAGE PROCESSING APPARATUS AND METHOD - An image processing apparatus for processing a previous image having first pixels and a present image having second pixels. The image processing apparatus includes: a pixel difference calculating unit which calculates pixel differences between corresponding pairs of the first and second pixels, and outputs pixel difference values; an edge processing unit which detects and compares edge types of the first and second pixels, sums a number of the edge types that are the same, and outputs a sum value; a noise level processing unit which calculates a noise level of the present image according to the sum value and the pixel differences; a blending value determining unit which determines a blending value according to the noise level; and an output unit which adds weights of the present and previous images according to the blending value and outputs an output image. An image processing method is also disclosed. | 04-29-2010 |
| 20120082379 | Image Adjustment Method and Device - An image adjustment method includes the steps of: a) configuring a weight-value generator to receive first image data and specified data and to generate an adaptive weight value according to the first image data and the specified data; and b) configuring an image blender to receive the first image data and second image data, and to generate adjusted image data by blending the first image data and the second image data with reference to the adaptive weight value. The adaptive weight value has a magnitude that corresponds to a difference between the first image data and the specified data. | 04-05-2012 |
Chun-I Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090283856 | METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE - A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer. | 11-19-2009 |
| 20090311878 | METHOD FOR DEPOSITING A DIELECTRIC MATERIAL - A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant. | 12-17-2009 |
| 20100021626 | METHOD OF FABRICATING RRAM - A method of fabricating a RRAM includes: forming a bottom electrode; forming a first metal layer, a first metal oxide layer, and a second metal layer on the bottom electrode in sequence; performing an RTO process followed by a top electrode formation; oxidizing the first metal layer to a second metal oxide layer comprising a second oxygen content; and oxidizing the second metal layer to a third metal oxide layer comprising a third oxygen content; wherein the first metal oxide layer has a first oxygen content after the RTO process is performed, the third oxygen content being higher than the first oxygen content and the first oxygen content being higher than the second oxygen content. | 01-28-2010 |
| 20100072449 | RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND METHOD OF MAKING THE SAME - A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light. | 03-25-2010 |
| 20100181545 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers. | 07-22-2010 |
| 20100193762 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening. | 08-05-2010 |
E. R. Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120126197 | Structure and process of basic complementary logic gate made by junctionless transistors - The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc. | 05-24-2012 |
Hsiao Hui Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100231254 | METHOD FOR CONFIGURING COMBINATIONAL SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR DEVICES USING THE SAME - A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second switching module to form the combinational switching matrix, building a connection mapping table based on the coupling relationship between the output port of the first switching module and the input port of the second switching module, and displaying a channel switching interface showing the input terminals, the output terminals, and the on/off states of the virtual switching devices of the combinational switching matrix. | 09-16-2010 |
Hsien-Cheng Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100097042 | LOW DROPOUT REGULATOR HAVING A CURRENT-LIMITING MECHANISM - A low dropout regulator having a current-limiting mechanism is disclosed. The regulator includes a sensing resistor, an error amplifier, and first through fourth transistors. The first transistor generates an output voltage according to an input voltage and a current control signal. The sensing resistor is employed to generate a sense voltage based on the current flowing through the fourth transistor so as to control the second transistor for generating an internal voltage. The third transistor controls the current control signal based on a voltage divided from the internal voltage. The channel width/length ratio of the first transistor is greater than that of the fourth transistor. When the third transistor is turned off, the error amplifier adjusts the voltage of the current control signal according to a voltage divided from the output voltage; when the third transistor is turned on, the voltage of the current control signal is not adjusted. | 04-22-2010 |
Hsin-Ju Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100330631 | Cis-aconitate Decarboxylase Mutants Having Improved Enzymatic Activity - Cis-aconitate decarboxylase mutants having one or more mutations in a C-terminal region as compared with a wild-type cis-aconitate decarboxylase of | 12-30-2010 |
| 20100330632 | Cis-aconitate Decarboxylase Mutants Having Improved Enzymatic Activity - Cis-aconitate decarboxylase mutants having one or more mutations in a C-terminal region as compared with a wild-type cis-aconitate decarboxylase of | 12-30-2010 |
Hui-Yen Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090195207 | Servo Control Circuit - The present invention discloses a servo control circuit comprising: a first node for receiving a control voltage; a second node for receiving a feedback voltage; an operational amplifier controlling a current on a path according to the voltages at the first and second nodes, the path including an internal voltage node thereon; an analog to digital converter (ADC) for converting the voltage at the internal voltage node to a digital signal; and a control logic circuit for generating a servo control signal according to the digital signal. | 08-06-2009 |
| 20110199029 | Bi-Direction Driver IC and Method for Bi-Directionally Driving an Object - The present invention discloses a bi-direction driver IC and a method for bi-directionally driving an object. The method comprises: providing a first and a second integrated circuit (IC) chips, coupled with an object to be driven, wherein each of the first and second IC chips is capable of single-directionally driving the object; providing a reverse current path in each of the first and second IC chips; driving the object in a first direction by the first IC chip, wherein current flows through the reverse current path in the second IC chip; and driving the object in a second direction by the second IC chip, wherein current flows through the reverse current path in the first IC chip. | 08-18-2011 |
Hung Chang Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100279234 | DOUBLE PATTERNING METHOD USING METALLIC COMPOUND MASK LAYER - A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer. | 11-04-2010 |
I-Lin Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110009060 | Systems and Methods for Reducing Interference Between a Plurality of Wireless Communications Modules - A wireless communications system is provided with a first wireless communications and a second wireless communications. The first wireless communications module transmits or receives a first wireless signal in a first frequency band selected from a first frequency range. The second wireless communications module transmits or receives a second wireless signal in a second frequency band selected from a second frequency range, and adjusts a transmission power of the second wireless signal in response to that a frequency offset between the first frequency band and the second frequency band falls within a predetermined range. | 01-13-2011 |
| 20110009074 | SYSTEMS AND METHODS FOR COEXISTENCE BETWEEN PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA - A system for the coexistence between a plurality of wireless communications modules sharing single antenna is provided. A wireless communications chipset includes a first wireless communications module configured to transmit or receive first wireless communications signals, and a second wireless communications module configured to transmit or receive second wireless communications signals. A path selection circuit is configured to connect the first wireless communications module to the antenna via a first transceiving path or a second transceiving path for transmitting and receiving the first wireless signals according to transceiving statuses of the first wireless signals and the second wireless signals. | 01-13-2011 |
| 20110310741 | APPARATUSES AND METHODS FOR COORDINATION BETWEEN PLURALITY OF CO-LOCATED WIRELESS COMMUNICATION MODULES VIA ONE WIRE - The invention provides a mobile communication device having a Packet Traffic Arbitrator (PTA) module and a first wireless communication module, coupled to the PTA module via only one wire and configured to perform a first wireless transceiving. The first wireless communication module sends a first request indicating a remaining period of time for a second wireless communication module to use to the PTA module via the wire, and receives, via the wire, a first response indicating whether the first request has been accepted. | 12-22-2011 |
Jui Hai Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100122657 | Electrode, Chemical Vapor Deposition Apparatus Including the Electrode and Method of Making - The present disclosure is directed to a chemical vapor deposition apparatus. The apparatus comprises a chamber having a gas inlet and a gas outlet. A first electrode is at least partially positioned in the chamber. The first electrode comprises an electrically conductive first portion and an electrically conductive second portion, the first portion being attached to the second portion by a first TIG weld bead. A second electrode is at least partially positioned in the chamber. The second electrode comprises an electrically conductive third portion and an electrically conductive fourth portion, the third portion being attached to the fourth portion by a second TIG weld bead. An electrode and a method of making the electrode are also disclosed. | 05-20-2010 |
| 20100147219 | HIGH TEMPERATURE AND HIGH VOLTAGE ELECTRODE ASSEMBLY DESIGN - A chemical vapor deposition apparatus is disclosed. The chemical vapor deposition apparatus comprises a chamber having a base plate, a chamber wall, a gas inlet and a gas outlet. The base plate has holes therethrough. A plurality of electrodes extend through the holes of the base plate. The plurality of electrodes are capable of being attached to a power source. At least two of the plurality of electrodes are capable of being electrically coupled to a silicon rod positioned in the chamber. An electrical isolation bushing can be positioned between each of the plurality of electrodes and the base plate. The electrical isolation bushing comprises a sleeve portion surrounding a portion of the electrodes that extends through the base plate and a collar portion surrounding the holes at a surface of the base plate. In some instances, the collar portion can comprise a different material than the sleeve portion. In some instances, an isolation layer can be employed in addition to the isolation bushing, the isolation layer surrounding the holes at the surface of the base plate. In some instances, the collar portion and the sleeve portion are both ceramic. | 06-17-2010 |
Jui Hai (harry) Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100101494 | ELECTRODE AND CHEMICAL VAPOR DEPOSITION APPARATUS EMPLOYING THE ELECTRODE - A chemical vapor deposition apparatus is disclosed. The chemical vapor deposition apparatus comprises a chamber having a base plate, a chamber wall, a gas inlet, a gas outlet and a plurality of electrodes each comprising an electrode body and an electrode cap removably attached to the electrode body. The electrode body can be positioned through the base plate. The cap can be positioned inside the chamber. An electrical isolation layer is positioned between the electrode and the base plate. The plurality of electrodes are capable of being attached to a power source. At least two of the plurality of electrodes are capable of being electrically coupled to a silicon rod positioned in the chamber. | 04-29-2010 |
Jung-Yu Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110073937 | Method for Fabricating a Charge Trapping Memory Device - A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer. | 03-31-2011 |
Jung-Yuan Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100081273 | METHOD FOR FABRICATING CONDUCTIVE PATTERN - A method for fabricating a conductive pattern including following steps is provided. A first conductive layer is formed on a substrate. A patterned hard mask layer is formed on the first conductive layer. A portion of the first conductive layer is removed to expose a portion of the substrate by using the patterned hard mask layer as a mask. A dielectric layer covering the patterned hard mask layer is formed on the substrate. A portion of the dielectric layer is removed to expose the patterned hard mask layer. The patterned hard mask layer is removed to form an opening in the dielectric layer. A second conductive layer is formed in the opening. | 04-01-2010 |
Junwei Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100278391 | Apparatus for behavior analysis and method thereof - In the present invention, an apparatus for behavior analysis and method thereof is provided. In this apparatus, each behavior is analyzed and has its corresponding posture sequence through a triangulation-based method of triangulating the different triangle meshes. The two important posture features, the skeleton feature and the centroid context, are extracted and complementary to each other. The outstanding ability of posture classification can generate a set of key postures for coding a behavior sequence to a set of symbols. Then, based on the string representation, a novel string matching scheme is proposed to analyze different human behaviors even though they have different scaling changes. The proposed method of the present invention has been proved robust, accurate, and powerful especially in human behavior analysis. | 11-04-2010 |
Jun-Wei Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120106802 | VEHICLE LICENSE PLATE RECOGNITION METHOD AND SYSTEM THEREOF - A vehicle license plate recognition method and a system thereof are disclosed. A region where a vehicle license plate image exists is detected according to the edge densities of an input image and a vehicle license plate specification. A text area of the vehicle license plate image is divided into a plurality of character images. The character images are binarized to obtain a plurality of binarized character images. A plurality of characters is recognized from the binarized character images. The characters are recombined to form a character string. The abovementioned steps are repeated to obtain a new character string from another image of the same vehicle, which is captured at a next time point. The character string is compared with the new character string character by character to obtain a comparison result for verifying reliability of recognition through a voting technique. | 05-03-2012 |
Kun-Hung Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080247284 | RECORDING APPARATUS FOR OPTICAL DISK DRIVE - A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal, the frequency of buffer under-run occurrence, the temperature of the drive, the wobble jitter and the level of write power is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. If at least one of the temperature of the drive, the wobble jitter and the estimated write power exceeds the reset value before recording starts, the rotation speed of the optical disk drive is decreased before recording. | 10-09-2008 |
| 20090080322 | RECORDING METHOD AND APPARATUS FOR OPTICAL DISK DRIVE - A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal and the frequency of buffer under-run occurrence is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. | 03-26-2009 |
Meng-Han Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090050904 | LIGHT EMITTING DIODE CIRCUIT - A light emitting diode circuit includes a chip and a light emitting diode. The chip includes a current control unit that is used for controlling a driving current flowing through a path. The light emitting diode is positioned outside of the chip and is coupled to the path. The light emitting diode generates a light source according to the driving current. The light emitting diode circuit can directly control the current value of a driving current flowing through the light emitting diode. In this way, the circuit design is simplified and the production cost of the electronic product is reduced. | 02-26-2009 |
| 20090190631 | METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF - A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence. | 07-30-2009 |
| 20090198754 | Order adaptive finite impulse response filter and operating method thereof - A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality. | 08-06-2009 |
Min-Hsun Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090146049 | OPTOELECTRONIC DEVICE ASSEMBLY - An embodiment of present invention discloses an optoelectronic device package including a first auxiliary energy receiver having a first energy inlet and a side wall for substantially directing energy far away from the first energy inlet; an optical element optically coupled to the first auxiliary energy receiver and having a recess facing the first energy inlet; and an optoelectronic device optically coupled to the optical element and receiving the energy from the first energy inlet. | 06-11-2009 |
| 20090302334 | Light-emitting element array - A light-emitting element array includes a conductive substrate; an adhesive layer disposed on the conductive substrate; a first epitaxial light-emitting stack layers disposed on the adhesive layer, the first epitaxial light-emitting stack layers including a first p-contact and an first n-contact, wherein the first p-contact and the first n-contact are disposed on the same side of the first epitaxial light-emitting stack layer; and a second epitaxial light-emitting stack layers disposed on the adhesive layer including a second p-contact and an second n-contact, wherein the second p-contact and the second n-contact are disposed on the opposite side of the epitaxial light-emitting stack layer; wherein the first epitaxial light-emitting stack layers and the second epitaxial light-emitting stack layers are electrically connected in anti-parallel. | 12-10-2009 |
| 20100213493 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first partial of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second partial of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 08-26-2010 |
| 20100308355 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 12-09-2010 |
| 20100314657 | OPTOELECTRONIC DEVICE - A optoelectronic device comprises a semiconductor stack layer; a first transparent conductive oxide (abbreviate as “TCO” hereinafter) layer located on the semiconductor stack layer, wherein the first TCO layer has at least one opening; and a second TCO layer covering the first TCO layer, wherein the second TCO layer is filled into the opening of the first TCO layer and contacted with the semiconductor stack layer, and one of the first TCO layer and the second TCO layer forms an ohmic contact with the semiconductor stack layer. | 12-16-2010 |
| 20110089444 | LIGHT-EMITTING ELEMENT - A light emitting element includes a carrier, a conductive connecting structure disposed on the carrier, an epitaxial stack structure including at least a first lighting stack and a second lighting stack disposed on the conductive connecting structure, an insulation section disposed between the epitaxial stack structure and the conductive connecting structure, and at least a metal line laid on the surface of the light emitting element, wherein the first light emitting stack further includes two electrodes having different polarity formed thereon; the second lighting stack is electrically connected to the conductive connecting structure at the bottom thereof and includes an electrode formed thereon. The insulation section is disposed below the first lighting stack to make the first lighting stack be insulated from the conductive connecting structure. The metal lines and the conductive connecting structure are electrically connected to each of the lighting stacks in parallel connection or series connection. | 04-21-2011 |
| 20110108879 | LIGHT-EMITTING DEVICE - A light-emitting device comprising a semiconductor light-emitting stack, comprising a light emitting area; an electrode formed on the semiconductor light-emitting stack, wherein the electrode comprises a current injected portion and an extension portion; a current blocking structure formed between the current injected portion and the semiconductor light-emitting stack, and formed between a first part of the extension portion and the semiconductor light-emitting stack; and an electrical contact structure formed between a second part of the extension portion and the semiconductor light-emitting stack. | 05-12-2011 |
| 20120012867 | MULTI-DIMENSIONAL LIGHT-EMITTING DEVICE - The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting device comprises a substrate, a blue light-emitting diode array and one or more phosphor layers. The blue light-emitting diode array, disposed on the substrate, comprises a plurality of blue light-emitting diode chips which are electrically connected. The multi-dimensional light-emitting device comprises a central area and a plurality of peripheral areas, which are arranged around the central area. The phosphor layer covers the central area. When the power supply system provides a high voltage, the central area and the peripheral areas of the multi-dimensional light-emitting device provide a first light and a plurality of second lights, respectively. The first light and the second lights are blended into a mixed light. | 01-19-2012 |
| 20120104455 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device includes a substrate and a first transition stack formed on the substrate including at least a first transition layer formed on the substrate and having at least one hollow component formed inside the first transition layer, and a second transition layer wherein the second transition layer is an unintentional doped layer or an undoped layer formed on the first transition layer. | 05-03-2012 |
Pai-Chu Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120062753 | IMAGE ENCODING INTEGRATED CIRCUIT AND ENCODED IMAGE DATA TRANSMISSION METHOD THEREOF - An image encoding integrated circuit and an encoded image data transmission method thereof are provided. The image encoding integrated circuit is utilized in a webcam and includes a central processing unit, an image sensing control unit, an image encoder unit, a bit rate monitoring unit, a transmission unit, and a bit rate control unit. The central processing unit, the image sensing control unit, the bit rate monitoring unit, and the transmission unit respectively produce a demand adjustment signal, a sensing status signal, a bit rate signal, and a transmission status signal. The bit rate control unit utilizes at least one of the signals to produce a quantization parameter signal. The image encoding unit transmits encoded image data in a specific bit rate, wherein the bit rate is adjusted according to the quantization parameter signal. The output bit rate of the image encoding unit is adjusted in consideration of even more system parameters, so as to improve the efficiency of the bit rate control. | 03-15-2012 |
Pao-Ju Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100110336 | OPTICAL ELEMENTS, BACKLIGHT MODULES, AND LIQUID CRYSTAL DISPLAY EMPLOYING THE SAME - Optical elements and backlight modules employing the same are provided. The optical element can be a brightness enhancement diffusion complex film, comprising a cholesteric liquid crystal film and a transparent optical film directly disposed on the cholesteric liquid crystal film. Particularly, the whole transparent optical film directly contacts to the cholesteric liquid crystal film, in the absence of an intermediate located between the transparent optical film and the cholesteric liquid crystal film. | 05-06-2010 |
| 20100321626 | BISTABLE DISPLAY MATERIALS AND METHODS AND DEVICES THEREOF - A display material and method and device thereof are provided. The display material is first formed by evenly mixing appropriate weight ratios of DFLCs, incurable nanoparticles, curable nanoparticles, and a photoinitiator. Next, the evenly mixed mixture is disposed between two parallel conducting transparent substrates, wherein an electrical field is conducted thereto and the DFLCs therein aligned to the direction of the applied electrical field. Concurrently, under the applied electrical field, some curable nanoparticles within the evenly mixed mixture, form short nano chains, initiating the photo initiator. The frame structure of short nano chains stabilize both the clear and scattering states, thereby the bistable characteristic was improved and the contrast ratio was enhanced as applied to bistable displays. | 12-23-2010 |
Tsung-Eong Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110079754 | Fabricating method of nano-powder and application thereof - A fabricating method of nano-powder is provided. First, a mixture having at least a first material and a second material is provided. Then, the mixture is sintered to obtain a single phase alloy body. After that, the single phase alloy body is pre-crumbled to obtain a powder to be ground. Then, a chemical dispersant is added into the powder to further be ground, so as to obtain the nano-powder. | 04-07-2011 |
Tsung-Fu Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100279436 | Inspection Method For Integrated Circuit Manufacturing Processes - The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron beam scan is then performed on the substrate. The electron beam scan includes a first scan and a second scan. The first scan includes a lower landing energy than the second scan. In an embodiment, the first scan provides a dark silicide image analysis and a bright image analysis. In an embodiment, the second scan provides a dark silicide image analysis. The method continues to form a conductive plug after performing the electron beam scan. | 11-04-2010 |
Tsung-Ying Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100207638 | Testing System and Testing Method - The invention discloses a testing system and a testing method. The testing system includes a testing platform and a fetching device. The testing platform includes a metal base plate, a DUT board, a testing stand and a metal wall. The DUT board is disposed on the metal base plate. The testing stand is disposed on the DUT board. The metal wall is disposed on the metal base plate and surrounds the testing stand. The fetching device is movably disposed above the testing platform and used for placing a DUT on the testing stand. A metal covering plate of the fetching device corresponds to the metal wall of the testing platform. When the fetching device places the DUT on the testing stand, the metal covering plate cooperates with the metal wall and the metal base plate of the testing platform to form an isolated space, so as to isolate the DUT. | 08-19-2010 |
| 20100289706 | WIRELESS COMMUNICATING DEVICE AND PORTABLE ELECTRONIC APPARATUS USING THE SAME - A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit. | 11-18-2010 |
Wei-Chih Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110221512 | Charge Pump - A charge pump is disclosed for amplifying an input voltage received at an input end and outputting the amplified voltage at an output end as an output voltage. The charge pump includes a plurality of source/drain coupling transistors for serving as charging capacitors, and a plurality of cascode-connected transistors being symmetrically connected to between the input end and the output end. The charge pump further includes a plurality of diode-connected transistors to protect the source/drain coupling transistors against breakdown during the course of charge transfer and to speed up the charge transfer. | 09-15-2011 |
Wei-Pin Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100240120 | ANALYTICAL STRIP AND THE MANUFACTURING METHOD THEREOF - An analytical strip including a substrate and a channel structure is disclosed. A substrate has a flat surface and the channel is formed on the flat surface according to a predetermined pattern. The surface of channel structure is not lower than the surface of the substrate. The channel has a hollow-matrix conformation and the channel is more hydrophilic than the flat surface of the substrate is. The strip also contains a reaction material formed in the hollow-matrix. | 09-23-2010 |
Wen-Chin Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090261914 | CRYSTAL OSCILLATOR CIRCUITS - An oscillator circuit. A gain stage element is coupled between both terminals of the crystal. The gain stage element provides a transconductance for oscillation according to a current provided by a current source, and outputs a periodic signal through an output terminal. A bias element is coupled between an input terminal and the output terminal of the gain stage element to bias the gain stage element. A first capacitor is coupled to the input terminal of the gain stage element. A second capacitor is coupled to the output terminal of the gain stage element. A controller detects the periodic signal, and adjusts the current when the periodic signal is obtained. | 10-22-2009 |
| 20100128177 | SIGNAL PROCESSING UNITS CAPABLE OF PROVIDING PLUG-IN DETECTION - Signal processing units capable of providing plug-in detection without an external circuit occupying GPIO resource are provided, in which a switching element is coupled to a television signal output pad, a terminal resistor is coupled between the switching element and a ground voltage, and an interrupt signal generator generates an interrupt signal when a receiving port of a television signal receiver is coupled to the television signal pad. A control unit turns on the switching element to connect the terminal resistor to the television signal output pad when receiving the interrupt signal, wherein the switching element, the terminal resistor, the interrupt signal generator and the control unit are integrated in a chip. | 05-27-2010 |
Wen-Yi Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080311713 | MOBILITY ENHANCEMENT BY STRAINED CHANNEL CMOSFET WITH SINGLE WORKFUNCTION METAL-GATE AND FABRICATION METHOD THEREOF - The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate. | 12-18-2008 |
Ying Hao Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110049567 | BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess. | 03-03-2011 |
Yuan-Chih Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080246152 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern. | 10-09-2008 |
| 20090039452 | EMBEDDED BONDING PAD FOR IMAGE SENSORS - A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer. | 02-12-2009 |
| 20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
| 20100087029 | METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate with a front surface and a back surface; forming a first alignment mark for global alignment on the front surface of the substrate; forming a second alignment mark for fine alignment in a clear-out region on the front surface of the substrate; aligning the substrate from the back surface using the first alignment mark; and removing a portion of the back surface of the substrate at the clear-out region for locating the second alignment mark. | 04-08-2010 |
| 20100151615 | METHODS FOR FABRICATING IMAGE SENSOR DEVICES - Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer. | 06-17-2010 |
| 20110156217 | POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MANUFACTURE - A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging. | 06-30-2011 |
| 20110159631 | METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference. | 06-30-2011 |
| 20110233621 | Wafer Level Packaging Bond - The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum. | 09-29-2011 |
| 20120025389 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 02-02-2012 |
| 20120074590 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided. | 03-29-2012 |
| 20120080761 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer. | 04-05-2012 |
| 20120091598 | HANDLING LAYER FOR TRANSPARENT SUBSTRATE - A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device. | 04-19-2012 |
Yu-Cheng Hsieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090240357 | METHOD FOR FINDING OUT THE FRAME OF A MULTIMEDIA SEQUENCE - An electronic device is provided comprising a multimedia play unit and a processor. The processor receives a multimedia sequence, acquires a first bitrate of a first frame header from the received multimedia sequence, predicts a first length of a first frame comprising the first frame header by a formula employing at least parameters comprising the first bitrate and a proportion of a second length to a second bitrate of a second frame header prior to the first frame header, and directs the multimedia play unit to play frame data of the first frame according to the predicted first length of the first frame. | 09-24-2009 |