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| 20100207671 | FREQUENCY DIVIDING CIRCUIT - A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals. | 08-19-2010 |
| 20100215130 | Method and Related Device for Detecting Signals in a TMDS Transmission System - A method for detecting signals in a TMDS transmission system is disclosed. A channel of the TMDS system is established between a receiver and a transmitter. The method includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference. | 08-26-2010 |
| 20100259106 | SWITCHING CONTROL METHOD CAPABLE OF CONTINUOUSLY PROVIDING POWER AND RELATED APPARATUS AND POWER SUPPLY SYSTEM - A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal. | 10-14-2010 |
| 20110012689 | Impedance Adjustment Circuit for Adjusting Terminal Resistance and Related Method - An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal. | 01-20-2011 |
| 20110032977 | Dual-Port Input Equalizer - A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit. | 02-10-2011 |
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| 20100321340 | System and Method of Distinguishing Multiple Touch Points - The invention discloses a method of distinguishing multiple touch points applied to an optical touch system which includes a panel for indicating a first touch point and a second touch point thereon and a camera unit for capturing an image relative to the first touch point and the second touch point. The image has a first dark area and a second dark area corresponding to the first touch point and the second touch point respectively. In the method, if it is observed that the first dark area and the second dark area merge into a first single dark area and a second single dark area at current time and previous time respectively, the respective positions of the first dark area and the second dark area are determined based on the respective union dark area widths of the first single dark area and the second single dark area, and the respective coordinates of the first touch point and the second touch point are determined according to the respective positions of the first dark area and the second dark area. | 12-23-2010 |
| 20110102376 | Image-Based Coordinate Input Apparatus and Method Utilizing Buffered Imates - The invention provides an image-based coordinate input apparatus and method for detecting positions of N objects on a coordinate input region at a detecting interval where N equals to 1 or 2. According to the invention, starting at the start of the detecting interval, successive first images at a first view and successive second images at a second view relative to the N objects and a background of the perimeter of the coordinate input region are captured and buffered. The apparatus and method according to the invention judges the number of the N objects and calculates the positions of the N objects on the coordinate input region at the detecting interval in accordance with the buffered successive first images and the buffered successive second images. | 05-05-2011 |
| 20110119579 | METHOD OF TURNING OVER THREE-DIMENSIONAL GRAPHIC OBJECT BY USE OF TOUCH SENSITIVE INPUT DEVICE - The invention provides a method of turning over a three-dimensional graphic object by use of a touch sensitive input device. In particular, the method according to the invention provides a user with intuitive operation on a touch sensitive surface of the touch sensitive input device to turn over whole or a portion (e.g., a page sub-object) of the three-dimensional graphic object. | 05-19-2011 |
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| 20110161690 | VOLTAGE SCALING SYSTEMS - A voltage scaling system is provided and includes a processor, a latency predictor, a controller, and a voltage supplier. The processor performs functions and includes a function unit with variable-latency. The function unit is divided into several power domains. When the processor performs the functions, the function unit generates a latency signal according to a current circuit execution speed. The latency predictor predicts performance of the processor according to the received latency signal to generate a predication signal. The controller compares a value of the predication signal with at least one reference value. The controller generates control signals according to the comparison result. The voltage supplier couples to a first voltage source providing a high voltage and a second voltage source providing a low voltage. The voltage supplier is switched to provide the high or low voltage to the power domains according to the control signals, respectively. | 06-30-2011 |
| 20110161719 | PROCESSING DEVICES - An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period. | 06-30-2011 |
| 20110314306 | PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF - A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal. | 12-22-2011 |
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| 20090021872 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 01-22-2009 |
| 20090097174 | ESD protection circuit for IC with separated power domains - An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node. | 04-16-2009 |
| 20090296293 | ESD PROTECTION CIRCUIT FOR DIFFERENTIAL I/O PAIR - An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events. | 12-03-2009 |
| 20100142107 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 06-10-2010 |
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| 20110174714 | Drainage fitting for air-conditioner drainage device - A drainage fitting is mounted to an air-conditioner drainage device having a waste collector provided with an inlet and an outlet. The drainage fitting is composed of a drainage connector having an annular protrusion externally and defining an upper part and a lower part, between which the annular protrusion is located, the lower part being mounted inside the outlet, the annular protrusion being stopped against the waste collector; at least two guide members being fixed to the waste collector and located at two opposite sides around the outlet and each has a guide recess facing the other, and a locating member having a hollow portion, against which the upper part of the drainage connector can be stopped, and having two sides be inserted into the guide recesses to lie against the annular protrusion. Accordingly, even if the drainage connector is accidentally forced to turn, it is disabled from separation from the waste collector. | 07-21-2011 |
| 20120112586 | MOTOR SHIELD FOR THE DRAINAGE DEVICE OF A COOLING OR AIR-CONDITIONING SYSTEM - A motor shield covered on a motor of a drainage device over a cooling vane is disclosed to include a shield body having an arched portion and a straight portion, a guide wall disposed in the shield body and having an arched segment and a straight segment connected to the straight portion of the shield body, an airflow zone defined in the shield body in an interference relationship relative to the cooling vane and surrounded by the arched segment and straight segment of the guide wall and the arched portion and straight portion of the shield body, horizontally extending air outlets and vertically extending air outlets respectively located on the arched portion and straight portion of the shield body, and air inlets located on the periphery of the shield body. During rotation of the cooling vane, a flow of air is induced to carry heat out of the shield body through the vertically and horizontally extending air outlets efficiently. | 05-10-2012 |
