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Hsiao-Che Wu

Hsiao-Che Wu, Jhongli TW

Patent application numberDescriptionPublished
20090189246METHOD OF FORMING TRENCH ISOLATION STRUCTURES AND SEMICONDUCTOR DEVICE PRODUCED THEREBY - A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′07-30-2009

Hsiao-Che Wu, Taoyuan Hsien TW

Patent application numberDescriptionPublished
20080316674Capacitors and methods for fabricating the same - Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.12-25-2008
20090127618MULTI-FIN FIELD EFFECT TRANSISTOR - A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.05-21-2009

Patent applications by Hsiao-Che Wu, Taoyuan Hsien TW

Hsiao-Che Wu, Chung-Li City TW

Patent application numberDescriptionPublished
20080199614Method for improving atomic layer deposition performance and apparatus thereof - A method for improving atomic layer deposition (ALD) performance and an apparatus thereof are disclosed. The apparatus alternates the process temperature of the different ALD steps rapidly, and the process temperature of each step is determined in accordance with the specific precursor and the substrate surface used. In case a higher process temperature is needed, a plurality of heating units of the apparatus increases and keeps the temperature of the deposited substrate to complete surface reaction. When the lower process temperature is needful for the next ALD step, the heating units are turned off to reduce the temperature of the deposited substrate and a gas flow puffed to the heater and the deposited substrate to assist in temperature cooling.08-21-2008
20090023264METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE - A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.01-22-2009
20090023268ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE - An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.01-22-2009
20090039428FABRICATING METHOD FOR SILICON ON INSULATOR AND STRUCTURE THEREOF - A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.02-12-2009
20090061635METHOD FOR FORMING MICRO-PATTERNS - A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.03-05-2009

Patent applications by Hsiao-Che Wu, Chung-Li City TW