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Hsiang-Yi
Hsiang-Yi Chen, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100053092 | Control Method for Touch Screen Device - A control method for a touch screen device is provided. The control method comprises the steps of: enabling an active mode of a touch panel; defining at least one active area on the touch panel; inputting a touch input into any one position on the touch panel; determining whether the touch input exists in the active area; and saving calculation of coordinate values of the position corresponding to the touch input and outputting a corresponding predetermined output signal in accordance with the touch input when the touch input exists in the active area. | 03-04-2010 |
| 20100321337 | METHOD FOR DETECTING TOUCH POSITION - An exemplary method for detecting touch position includes the steps of: detecting a plurality of sensing points, obtaining at least one first signal and a plurality of second signals on the sensing points, wherein the at least one first signal each has an energy above a preset threshold, the second signals each has an energy below the preset threshold, positions of the sensing points where the second signals being detected are successive with a position(s) of the sensing point(s) where the at least one first signal being detected; performing a weighted averaging operation applied to the energies of the at least one first signal and the second signals and taking a result of the weighted averaging operation as a first dimension coordinate of a touching point, wherein weights of the respective energies are associated with the positions of the sensing points where the at least one first signal and the second signals being detected. | 12-23-2010 |
Hsiang-Yi Chen, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100039405 | Projective Capacitive Touch Apparatus, and Method for Identifying Distinctive Positions - A projective capacitive touch apparatus and a method for identifying multi-touched positions are provided. The multi-touched positions are touched on a projective capacitive touch panel. The method comprises the following steps: generating a first set of reference values according to the first touch position; generating a plurality of second sets of reference values according to a second touch position, and filtering out at least one ghost second set of reference values from the second sets of reference values. Furthermore, the plurality of second sets of reference values comprise a real second set of reference value and at least one ghost second set of reference values, while the ghost second set of reference values comprises parts of the first set of reference values. | 02-18-2010 |
Hsiang-Yi Hsieh, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120096422 | RE-ROUTING METHOD FOR CIRCUIT DIAGRAM - A re-routing method for a circuit diagram includes the following steps. At least one pair of the signal lines is obtained from a routed circuit diagram. The routed circuit diagram is adapted to be laid out on a substrate of a Printed Circuit Board (PCB). The substrate includes warp wires and weft wires. At least one pair of the signal lines includes two signal lines in parallel. The pair of signal lines includes several pairs of line segments. It is determined whether at least one pair of parallel line segments exists in the pairs of line segments parallel to the warp or weft wires. If at least one pair of parallel line segments exists, at least one pair of parallel line segments on the routed circuit diagram is replaced with several pairs of 10-degree lines. Respective angle between the 10-degree lines and the warp or weft wires are 10 degrees. | 04-19-2012 |
Hsiang-Yi Huang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100153766 | MEMORY CONTROLLER AND DEVICE WITH DATA STROBE CALIBRATION - A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted. | 06-17-2010 |
Hsiang-Yi Wang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100052066 | STRUCTURE AND METHOD FOR A CMOS DEVICE WITH DOPED CONDUCTING METAL OXIDE AS THE GATE ELECTRODE - A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer. | 03-04-2010 |
| 20100084718 | ADVANCED METAL GATE METHOD AND DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure. | 04-08-2010 |
| 20110062526 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer. | 03-17-2011 |
Hsiang-Yi Yu, Taoyuan Coutny TW
| Patent application number | Description | Published |
|---|---|---|
| 20110256657 | METHOD OF ENCAPSULATING PHOTOVOLTAIC PANEL - Melted encapsulant is extruded directly onto the photovoltaic panel to encapsulate a photovoltaic panel. | 10-20-2011 |