| Patent application number | Description | Published |
|---|
| 20090057641 | Phase Change Memory Cell With First and Second Transition Temperature Portions - A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed. | 03-05-2009 |
| 20090098678 | VACUUM JACKETED ELECTRODE FOR PHASE CHANGE MEMORY ELEMENT - A memory device having a vacuum jacket around the first electrode element for improved thermal isolation. The memory unit includes a first electrode element; a phase change memory element in contact with the first electrode element; a dielectric fill layer surrounding the phase change memory element and the first electrode element, wherein the dielectric layer is spaced from the first electrode element to define a chamber between the first electrode element and the dielectric fill layer; and wherein the phase change memory layer is sealed to the dielectric fill layer to define a thermal isolation jacket around the first electrode element. | 04-16-2009 |
| 20090098716 | METHOD FOR MAKING A SELF-CONVERGED MEMORY MATERIAL ELEMENT FOR MEMORY CELL - A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second layer. A keyhole opening is formed through the upper layer to expose the bottom electrode. The first layer has an overhanging portion extending into the opening. A dielectric material is deposited into the keyhole opening so to create a self-converged void within the keyhole opening. An anisotropic etch forms a sidewall of the dielectric material in the keyhole opening with an electrode hole aligned with the void and exposing the bottom electrode. A memory material is deposited into the electrode hole in contact with the bottom electrode and is planarized down to the third layer to create the memory material element. | 04-16-2009 |
| 20090104771 | METHOD FOR MAKING A SELF-CONVERGED VOID AND BOTTOM ELECTRODE FOR MEMORY CELL - A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer. | 04-23-2009 |
| 20090140230 | Memory Cell Device With Circumferentially-Extending Memory Element - A memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element may directly contact said contact. | 06-04-2009 |
| 20100055830 | I-SHAPED PHASE CHANGE MEMORY CELL - A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member. | 03-04-2010 |
| 20100065808 | PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING - An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned. | 03-18-2010 |
| 20100068878 | THIN FILM FUSE PHASE CHANGE CELL WITH THERMAL ISOLATION PAD AND MANUFACTURING METHOD - A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode extends outwardly from the top sides of the first and second electrodes defining a wall of insulating material having top side. A bridge of memory material crosses the insulating member over the top of the wall, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises an active layer of memory material on the top side of the wall, having at least two solid phases and a layer of thermal insulating material overlying the memory material having thermal conductivity less than a thermal conductivity of the first and second electrodes. | 03-18-2010 |
| 20100072447 | PHASE CHANGE MEMORY CELL HAVING INTERFACE STRUCTURES WITH ESSENTIALLY EQUAL THERMAL IMPEDANCES AND MANUFACTURING METHODS - A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures. | 03-25-2010 |
| 20100133500 | Memory Cell Having a Side Electrode Contact - Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom. | 06-03-2010 |
| 20100144128 | Phase Change Memory Cell and Manufacturing Method - A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion. | 06-10-2010 |
| 20100151652 | MULTI-LEVEL MEMORY CELL HAVING PHASE CHANGE ELEMENT AND ASYMMETRICAL THERMAL BOUNDARY - A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes. | 06-17-2010 |
| 20100157665 | MEMORY CELL DEVICE AND PROGRAMMING METHODS - A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value. | 06-24-2010 |
| 20100165728 | PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode. | 07-01-2010 |
| 20100237316 | 4F2 SELF ALIGN SIDE WALL ACTIVE PHASE CHANGE MEMORY - Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F | 09-23-2010 |
| 20100261329 | MEMORY DEVICE HAVING WIDE AREA PHASE CHANGE ELEMENT AND SMALL ELECTRODE CONTACT AREA - A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described. | 10-14-2010 |
| 20100265773 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 10-21-2010 |
| 20100291747 | Phase Change Memory Device and Manufacturing Method - A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size. | 11-18-2010 |
| 20100297824 | MEMORY STRUCTURE WITH REDUCED-SIZE MEMORY ELEMENT BETWEEN MEMORY MATERIAL PORTIONS - A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer. | 11-25-2010 |
| 20100328995 | METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY - Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics. | 12-30-2010 |
| 20100328996 | PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions. | 12-30-2010 |
| 20110013446 | REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array. | 01-20-2011 |
| 20110017970 | SELF-ALIGN PLANERIZED BOTTOM ELECTRODE PHASE CHANGE MEMORY AND MANUFACTURING METHOD - A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers. | 01-27-2011 |
| 20110034003 | Vacuum Cell Thermal Isolation for a Phase Change Memory Device - A memory device with improved thermal isolation. The memory cell includes a first electrode element, having an upper surface; an insulator stack formed on the first electrode element, including first, second and third insulating members, all generally planar in form and having a central cavity formed therein and extending therethrough, wherein the second insulator member is recessed from the cavity; a phase change element, generally T-shaped in form, having a base portion extending into the cavity to make contact with the first electrode element and making contact with the first and third insulating members, and a crossbar portion extending over and in contact with the third insulating member, wherein the base portion of the phase change element, the recessed portions of the second insulating member and the surfaces of the first and third insulating members define a thermal isolation void; and a second electrode formed in contact with the phase change member. | 02-10-2011 |
| 20110049456 | PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY - A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region. | 03-03-2011 |
| 20110063902 | 2T2R-1T1R MIX MODE PHASE CHANGE MEMORY ARRAY - A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell. | 03-17-2011 |
| 20110068418 | SUBSTRATE SYMMETRICAL SILICIDE SOURCE/DRAIN SURROUNDING GATE TRANSISTOR - Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements. | 03-24-2011 |
| 20110076825 | Method for Making a Self Aligning Memory Device - A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width. | 03-31-2011 |
| 20110084397 | 3D INTEGRATED CIRCUIT LAYER INTERCONNECT - A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided. | 04-14-2011 |
| 20110116308 | MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - An integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics, such as switching speeds, retention and endurance. | 05-19-2011 |
| 20110116309 | Refresh Circuitry for Phase Change Memory - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array. | 05-19-2011 |
| 20110133150 | Phase Change Memory Cell with Filled Sidewall Memory Element and Method for Fabricating the Same - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element. | 06-09-2011 |
| 20110163288 | Manufacturing Method for Pipe-Shaped Electrode Phase Change Memory - A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described. | 07-07-2011 |
| 20110165753 | Method for Making Self Aligning Pillar Memory Cell Device - A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed. | 07-07-2011 |
