| Patent application number | Description | Published |
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| 20080272994 | APPARATUS FOR CONTROLLING THE LIQUID CRYSTAL DISPLAY - An apparatus for controlling an LCD is provided. The apparatus includes a memory, an image scaler circuit, a liquid crystal accelerating circuit, an image stretcher circuit, and an interface signal transmitting circuit. A first frame data is stored in the memory. The image scaler circuit receives and shrinks a second frame data. The liquid crystal accelerating circuit is coupled to the image scaler circuit, the memory, and the image stretcher circuit for comparing the first and the second frame data and adjusting pixels of the second frame data. The apparatus refreshes the first frame data stored in the memory with the second frame data. The image stretcher circuit enlarges the adjusted second frame data, and transmits an interface signal to a liquid crystal panel module through the interface signal transmitting circuit. The present invention drives the liquid crystal panel module to achieve the output maximum resolution with minimum required memory. | 11-06-2008 |
| 20090015296 | DIGITAL FREQUENCY SYNTHESIZER AND METHOD THEREOF - A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved. | 01-15-2009 |
| 20090021499 | DISPLAY DRIVING APPARATUS AND METHOD THEREOF - A display driving apparatus and a method thereof are provided. The apparatus includes a memory unit, a compression and decompression unit, a data selection unit, and a display accelerating unit. The memory unit is coupled to the compression and decompression unit and stores only a compressed frame to save memory space in the apparatus. The data selection unit determines whether an error is caused to a frame through data compression and decompression. When the error is greater than a predetermined value, the display accelerating unit turns off an overdriving process upon the pixels to avoid image distortion. The data selection unit also determines whether the frames are static or dynamic in order to determine whether to turn on the overdriving process. | 01-22-2009 |
| 20110050681 | LOW VOLTAGE DIFFERENTIAL SIGNAL OUTPUT STAGE - A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal. | 03-03-2011 |
| Patent application number | Description | Published |
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| 20100003774 | METHOD FOR FABRICATING PIXEL STRUCTURE - A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed. | 01-07-2010 |
| 20100003792 | METHOD FOR FABRICATING PIXEL STRUCTURE - A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed. | 01-07-2010 |
| 20100087021 | METHOD OF FABRICATING PIXEL STRUCTURE - A method of fabricating a pixel structure includes first forming a first, a second, and a third dielectric layers over an active device and a substrate. Etching rates of the first and the third dielectric layers are lower than an etching rate of the second dielectric layer. A contact opening exposing a portion of the active device is formed in the third, the second, and the first dielectric layers. The third and the second dielectric layers are patterned to form a number of stacked structures. An electrode material layer is formed and fills the contact opening. The electrode material layer located on the stacked structures and the electrode material layer located on the first dielectric layer are separated. The stacked structures and the electrode material layer thereon are simultaneously removed to define a pixel electrode and to form at least an alignment slit in the pixel electrode. | 04-08-2010 |
