| Patent application number | Description | Published |
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| 20080313533 | DYNAMICALLY LAYING OUT IMAGES AND ASSOCIATED TEXT USING PRE-DEFINED LAYOUTS - Technologies are described herein for dynamically laying out images and associated text using pre-defined layouts. The pre-defined layouts are created and data defining the layouts is stored in a layout definition file. An application program provides a user interface for dynamically laying out the images and associated text using the contents of the layout definition file. The user interface includes a canvas onto which a user may place one or more images and a layout gallery through which a user may select a pre-defined layout to be applied to images placed on the canvas. The layout gallery includes selectable visual representations corresponding to each of the available pre-defined layouts. When one of the visual representations is selected, the corresponding pre-defined layout is dynamically applied to images on the canvas. The visual representations displayed in the layout gallery may also be utilized to generate a preview of the layout. | 12-18-2008 |
| 20080313572 | Presenting and Navigating Content Having Varying Properties - Technologies are described herein for presenting and navigating content having varying properties. One or more local or networked providers are searched for content objects. Content objects include associated metadata and may be stored within a content container. Each content object is displayed separately from its associated content container. Displayed content objects may be grouped and filtered based upon the associated metadata. Displayed content objects may also be grouped and filtered based upon the provider from which they were retrieved. Selection of a content object causes the content container associated with the selected content object to be displayed. Alternately, selection of a content object may cause a preview of the selected content object and the metadata associated with the selected content object to be displayed. | 12-18-2008 |
| 20100171754 | CONVERTING DIGITAL INK TO SHAPES AND TEXT - A shape expressed using digital ink is recognized and a beautified shape is inserted into a document in a native document format. A user interface (“UI”) control is displayed adjacent to the beautified shape which, when selected, will display selectable items for modifying the beautified shape. Insertion of the beautified shape may be undone, the beautified shape may be deleted, and the format of the beautified shape may be modified. Digital ink may also be received that corresponds to text. The digital ink is inserted into a document, displayed, and the text represented by the digital ink is recognized. A UI control is displayed adjacent to the digital ink that will display one or more selectable UI items corresponding to recognition alternates. When selected, the selectable items will cause the text of the corresponding recognition alternate to be inserted into the document. | 07-08-2010 |
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| 20090158077 | Circuit and method for generation of duty cycle independent core clock - A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock. | 06-18-2009 |
| 20090185430 | Memory sensing and latching circuit - According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal. | 07-23-2009 |
| 20100246281 | Sensing and latching circuit for memory arrays - According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal. | 09-30-2010 |
