Patent application number | Description | Published |
20080266984 | Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 10-30-2008 |
20080273393 | Programmable Heavy-Ion Sensing Device for Accelerated Dram Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 11-06-2008 |
20090184264 | LASER ANNEALING FOR 3-D CHIP INTEGRATION - A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously. | 07-23-2009 |
20090309136 | SEA-OF-FINS STRUCTURE OF A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION - A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device. | 12-17-2009 |
20100293512 | CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT - Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips. | 11-18-2010 |
20110002188 | Apparatus for Nonvolatile Multi-Programmable Electronic Fuse System - Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system. | 01-06-2011 |
20110019321 | LEAKAGE SENSOR AND SWITCH DEVICE FOR DEEP-TRENCH CAPACITOR ARRAY - A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process. | 01-27-2011 |
20110201199 | LASER ANNEALING FOR 3-D CHIP INTEGRATION - A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously. | 08-18-2011 |
20120043597 | SEA-OF-FINS STRUCTURE ON A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION - A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device. | 02-23-2012 |
20120146845 | Narrow-Band Wide-Range Frequency Modulation Continuous Wave (FMCW) Radar System - A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal. | 06-14-2012 |