| Patent application number | Description | Published |
|---|
| 20090047783 | METHOD OF REMOVING UNWANTED PLATED OR CONDUCTIVE MATERIAL FROM A SUBSTRATE, AND METHOD OF ENABLING METALLIZATION OF A SUBSTRATE USING SAME - A method of removing unwanted material from a substrate includes providing a system ( | 02-19-2009 |
| 20090081381 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 03-26-2009 |
| 20090084598 | CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - Disclosed are a coreless substrate and a method of manufacturing the same. The coreless substrate includes a solder resist layer capable of being formed on each of on a first side and a second side of a metal panel. The solder resist layer includes at least one opening. A copper layer may be plated in the at least one opening such that a height of the copper layer exceeds a height of the solder resist layer. Further, at least one dielectric layer is deposited above the copper layer, and at least one microvia drilled in the dielectric layer. The at least one microvia enables an electrical connection between at least one of the first side and the second side of the metal panel and a lower surface of the coreless substrate. | 04-02-2009 |
| 20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 04-30-2009 |
| 20090152743 | ROUTING LAYER FOR A MICROELECTRONIC DEVICE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF FORMING A MULTI-THICKNESS CONDUCTOR IN SAME FOR A MICROELECTRONIC DEVICE - A routing layer for a microelectronic device includes a first region ( | 06-18-2009 |
| 20090166320 | SELECTIVE ELECTROLESS PLATING FOR ELECTRONIC SUBSTRATES - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed. | 07-02-2009 |
| 20090238233 | OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES - Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers. | 09-24-2009 |
| 20090238516 | SUBSTRATES FOR OPTICAL DIE STRUCTURES - Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard. | 09-24-2009 |
| 20090246462 | METHOD OF MANUFACTURING A SUBSTRATE FOR A MICROELECTRONIC DEVICE, AND SUBSTRATE FORMED THEREBY - A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material ( | 10-01-2009 |
| 20090314538 | Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same - A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface. | 12-24-2009 |
| 20110123725 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 05-26-2011 |
| 20110135883 | METHOD OF MANUFACTURING A SUBSTRATE FOR A MICROELECTRONIC DEVICE, AND SUBSTRATE FORMED THEREBY - A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material ( | 06-09-2011 |
| 20110147439 | Microelectronic device substrate fabrication - The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated. | 06-23-2011 |
