Patent application number | Description | Published |
20110278891 | MODULAR CONTOUR SUPPORT APPARATUS - A four way lumbar support for an automobile seat includes a wire array, a fixed frame, and a basculating arm. When in its extended position, the basculating arm exerts pressure on the wire array thus providing lumbar support to the seat occupant at that point. A system of cables and sliding connections allows the basculating arm to slide along the fixed frame so that the lumbar support may be provided at different heights within the seat. | 11-17-2011 |
20130306161 | SYSTEM AND METHOD FOR A PRESSURE SIGNAL LINEARIZATION TRANSFER FUNCTION - A method for operating a pneumatic lumbar support between a deflated position and an inflated position. The method includes inflating a bladder of the pneumatic lumbar support; sensing a pressure within the bladder using a pressure sensor; producing an inflation output signal from the pressure sensor, wherein the inflation output signal is a function of time; and converting the inflation output signal using an inflation-deflation transfer function. | 11-21-2013 |
20140070583 | LUMBAR SUPPORT SYSTEM - A lumbar support system for a seat backrest having a fixed frame includes a lumbar support coupled to the fixed frame that is movable from a first position to a second position and a motor for moving the lumbar support. A threaded member is operatively associated with the motor such that the motor rotates the threaded member about an axis. A traveling member is operatively associated with the threaded member such that rotation of the threaded member translates the traveling member along the threaded member. The system further includes a flexible cable having a first end and a second end. The first end is coupled to the traveling member for movement therewith and the second end is coupled to the fixed frame such that translation of the traveling member in response to rotation of the threaded member moves the lumbar support element from the first position to the second position. | 03-13-2014 |
20140070584 | LUMBAR SUPPORT SYSTEM - A lumbar support system for a seat backrest having a fixed frame includes a lumbar support coupled to the fixed frame that is movable from a first position to a second position and a motor for moving the lumbar support. A threaded member is operatively associated with the motor such that the motor rotates the threaded member about an axis. A traveling member is operatively associated with the threaded member such that rotation of the threaded member translates the traveling member along the threaded member. The system further includes a flexible cable having a first end and a second end. The first end is coupled to the traveling member for movement therewith and the second end is coupled to the fixed frame such that translation of the traveling member in response to rotation of the threaded member moves the lumbar support element from the first position to the second position. | 03-13-2014 |
20140125102 | LUMBAR SUPPORT SYSTEM - An adjustable support system for a seat having a fixed frame includes a support movable from a first position to a second position relative to the frame. An actuator is coupled to only the support and is configured to move the support between the first and second positions. A member is operatively associated with and movable by the actuator. A flexible cable has a first end coupled to the member for travel along the length of the member and a second end coupled to the fixed frame such that movement of the member by the actuator causes the flexible cable to move the support between the first position and the second position. | 05-08-2014 |
20140191553 | CABLE SYNCHRONIZER SYSTEM - An actuation system for concurrently actuating a first mechanism and a second mechanism from a first state to a second state includes an actuator and a sliding member operatively engaged with the actuator and movable from a first position to a second position in response to actuation of the actuator. A connecting member has a relaxed state and a taut state. The connecting member includes a first end coupled to the first mechanism, a second end coupled to the second mechanism, and a medial portion cooperative with the sliding member. Movement of the sliding member from the first position to the second position changes the connecting member from the relaxed state to the taut state, whereby the tension is increased in the connecting member. | 07-10-2014 |
20140265991 | SYSTEM AND METHOD FOR SENSORLESS REMOTE RELEASE ACTUATING SYSTEM - A method for configuring a controller to operate a motor to position a seat, in which the controller includes an integrated current sensor and the seat includes a latch operatively coupled to the motor, includes determining an operating profile of the motor under one or more operating conditions, wherein the operating profile represents motor current values during activation of the latch, and wherein the activation of the latch includes at least one latch pulling condition and one latch release condition. The method further includes analyzing the operating profile in order to correlate the profile to the position of the latch. The method also includes loading the controller with instructions to enable comparison of a real-time current measured by the integrated current sensor to the stored operating profile, wherein the analysis enables determination of the latch condition in real-time. | 09-18-2014 |
Patent application number | Description | Published |
20110222696 | CONFIGURABLE ELECTRONIC DEVICE REPROGRAMMABLE TO MODIFY THE DEVICE FREQUENCY RESPONSE - A test signal generator provides a test signal to an acoustic device under test and a data acquisition device acquires data from the acoustic device. The initial frequency response of the signal path through the acoustic device is determined based on the test signal and the acquired data. A target frequency response is selected. A desired configuration of a configurable circuit in the signal path is determined modifying the signal path such that the frequency response of the signal path is substantially similar to the target frequency response. At least one parameter for at least one programmable component of the configurable circuit is determined and programmed into the programmable component. | 09-15-2011 |
20130194034 | UNIVERSAL FILTER IMPLEMENTING SECOND-ORDER TRANSFER FUNCTION - An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks. | 08-01-2013 |
20140333372 | UNIVERSAL FILTER IMPLEMENTING SECOND-ORDER TRANSFER FUNCTION - An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks. | 11-13-2014 |
20150244363 | LINE RECEIVER CIRCUIT WITH ACTIVE TERMINATION - A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources. Finally, the feedback circuit also includes a differential amplifier that compares the output of the first current source to a reference value then generates the first voltage output to control each of the first and second current sources. | 08-27-2015 |
Patent application number | Description | Published |
20130042064 | SYSTEM FOR DYNAMICALLY ADAPTIVE CACHING - The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space. | 02-14-2013 |
20130339786 | SMART ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS - A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache Miss. The hot I/O data includes hot read data that accumulated dynamically regardless of ownership of the drives where the hot read data is permanently stored. The hot I/O data also includes hot write data that is mirrored across the solid state cache memories to avoid potential dirty write data conflicts and also to provide High Availability in case of server failures. | 12-19-2013 |
20140089545 | LEASED LOCK IN ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS - A method and system for IO processing in a storage system is disclosed. In accordance with the present disclosure, a controller may take long term “lease” of a portion (e.g., an LBA range) of a virtual disk of a RAID system and then utilize local locks for IOs directed to the leased portion. The method and system in accordance with the present disclosure eliminates inter-controller communication for the majority of IOs and improves the overall performance for a High Availability Active-Active DAS RAID system. | 03-27-2014 |
20140208005 | System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache - A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information. | 07-24-2014 |
20140208024 | System and Methods for Performing Embedded Full-Stripe Write Operations to a Data Volume With Data Elements Distributed Across Multiple Modules - A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation. | 07-24-2014 |
20140223071 | METHOD AND SYSTEM FOR REDUCING WRITE LATENCY IN A DATA STORAGE SYSTEM BY USING A COMMAND-PUSH MODEL - A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency. | 08-07-2014 |
20140223094 | SELECTIVE RAID PROTECTION FOR CACHE MEMORY - A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe. | 08-07-2014 |
20140244902 | FAST READ IN WRITE-BACK CACHED MEMORY - An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state. | 08-28-2014 |
20150286438 | System, Method and Computer-Readable Medium for Dynamically Configuring an Operational Mode in a Storage Controller - A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation. | 10-08-2015 |
20150347310 | Storage Controller and Method for Managing Metadata in a Cache Store - A cache controller coupled to a cache store supported by a solid-state memory element uses a metadata update process that reduces write amplification caused by writing both cache data and metadata to the solid-state memory element. The cache controller partitions the solid-state memory element to include a metadata portion, a host data or cache portion and a log portion. Host write requests that include “hot” data are processed and recorded by the cache controller. The cache controller maintains first and second maps. A log thread combines multiple metadata updates in a single log entry block. Pending metadata updates are checked to determine when a commit threshold is reached. Thereafter, the pending metadata updates are written to the solid-state memory element and the maps are updated. | 12-03-2015 |