Patent application number | Description | Published |
20090170260 | Non-Volatile Memory Cell Circuit With Programming Through Band-To-Band Tunneling And Impact Ionization Gate Current - Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described. | 07-02-2009 |
20090238008 | Non-Volatile Memory Cell With BTBT Programming - A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels. | 09-24-2009 |
20110255348 | Non-Volatile Memory Cell with BTBT Programming - A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor. | 10-20-2011 |
20120086068 | METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES - A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate. | 04-12-2012 |
20120205734 | Very Dense NVM Bitcell - An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step. | 08-16-2012 |
20130026553 | NVM Bitcell with a Replacement Control Gate and Additional Floating Gate - Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell. | 01-31-2013 |
20130135933 | RFID TAG HAVING NON-VOLATILE MEMORY DEVICE HAVING FLOATING-GATE FETS WITH DIFFERENT SOURCE-GATE AND DRAIN-GATE BORDER LENGTHS - Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length. | 05-30-2013 |
20130193498 | Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 08-01-2013 |
20130193501 | Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 08-01-2013 |
20140056076 | VERY DENSE NONVOLATILE MEMORY BITCELL - An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step. | 02-27-2014 |
20150034909 | ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR - A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations. | 02-05-2015 |
20150085585 | NVM DEVICE USING FN TUNNELING WITH PARALLEL POWERED SOURCE AND DRAIN - A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations. | 03-26-2015 |
Patent application number | Description | Published |
20120101595 | COMMUNICATION INTERFACE FOR SENSORY STIMULATION - Techniques, apparatuses, and systems for interfacing multiple sensors with a biological system can include amplifying signals from respective sensors associated with an external device; modulating the amplified signals based on respective different frequency values; and summing the modulated signals to produce an output signal to stimulate a biological system. | 04-26-2012 |
20140128951 | Modular Multi-Channel Inline Connector System - A modular multi-channel inline connector system that connects an implanted electrode within a body of an organism, such as the human body, with a device located external to or implanted within the body. The modular multi-channel inline system comprises of a first lead operatively connected to the implanted electrode and to a first connector portion. A second lead is operatively connected to a second connector portion and operatively connected to the device. One of the first and second connector portions comprises a male connector and the other of the first and second connector portions comprises a female connector. The first and second connector portions are arranged to connect with each other and to be operatively located embedded within the body. | 05-08-2014 |
20140236176 | Method for mapping sensor signals to output channels for neural activation - A method for mapping sensor signals to stimulation values and a device using the same are disclosed. The method includes the steps of receiving sensor signal from sensors, mapping the sensor signals to stimulation values, and delivering stimulation signals based on the stimulation values. The mapping may be performed using a linear, piecewise linear, or non-linear function. The method may be incorporated in an advanced prosthetic system that activates sensory neurons in a residual limb to provide an amputee with sensations related to grip force and hand opening. The method for implementing sensory feedback may also be incorporated into mechanical or robotic devices such as those used for surgery, games, and/or tele-manipulation. | 08-21-2014 |