Patent application number | Description | Published |
20100052745 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 03-04-2010 |
20100054055 | DATA INPUT/OUTPUT CIRCUIT - A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission line unit having a clock tree structure for transmitting the internal clock to the output unit, a second transmission line unit for transmitting the internal clock from the delay locked loop to the first transmission line unit, a duty cycle ratio correcting unit interconnected between the first transmission line unit and the second transmission line unit for correcting a duty cycle ratio of the internal clock, a data strobe signal input unit for receiving a second data strobe signal from an outside of a semiconductor memory device and generating an internal data strobe signal, and a plurality of data input units for outputting a second data in response to the internal data strobe signal. | 03-04-2010 |
20100295588 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal. | 11-25-2010 |
20110018600 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 01-27-2011 |
20110074478 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for reducing unnecessary current consumption disclosed. The semiconductor apparatus includes: a clock signal transmission unit that selectively transmits a clock signal in accordance with the frequency of the clock signal at an operation standby mode. A delay locked loop generates a DLL clock signal on the basis of the clock signal inputted through the clock signal transmission unit. The delay locked loop generates the DLL clock signal during a period where the clock signal is transmitted. | 03-31-2011 |
20110095797 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal. | 04-28-2011 |
20120007639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals. | 01-12-2012 |
20120007645 | DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock. | 01-12-2012 |