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| 20100052745 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 03-04-2010 |
| 20100054055 | DATA INPUT/OUTPUT CIRCUIT - A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission line unit having a clock tree structure for transmitting the internal clock to the output unit, a second transmission line unit for transmitting the internal clock from the delay locked loop to the first transmission line unit, a duty cycle ratio correcting unit interconnected between the first transmission line unit and the second transmission line unit for correcting a duty cycle ratio of the internal clock, a data strobe signal input unit for receiving a second data strobe signal from an outside of a semiconductor memory device and generating an internal data strobe signal, and a plurality of data input units for outputting a second data in response to the internal data strobe signal. | 03-04-2010 |
| 20100295588 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal. | 11-25-2010 |
| 20110018600 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 01-27-2011 |
| 20110074478 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for reducing unnecessary current consumption disclosed. The semiconductor apparatus includes: a clock signal transmission unit that selectively transmits a clock signal in accordance with the frequency of the clock signal at an operation standby mode. A delay locked loop generates a DLL clock signal on the basis of the clock signal inputted through the clock signal transmission unit. The delay locked loop generates the DLL clock signal during a period where the clock signal is transmitted. | 03-31-2011 |
| 20110095797 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal. | 04-28-2011 |
| 20120007639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals. | 01-12-2012 |
| 20120007645 | DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock. | 01-12-2012 |
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| 20090177820 | CONTROL BUS FOR CONNECTION OF ELECTRONIC DEVICES - A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus. | 07-09-2009 |
| 20090178097 | METHOD, APPARATUS AND SYSTEM FOR GENERATING AND FACILITATING MOBILE HIGH-DEFINITION MULTIMEDIA INTERFACE - A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled with the transmitter, the receiver configured to receive the single channel, and to unmerge the single channel into the multiple channels. | 07-09-2009 |
| 20090219447 | METHOD, APPARATUS, AND SYSTEM FOR DECIPHERING MEDIA CONTENT STREAM - A method, apparatus and system for media content deciphering is disclosed. In one embodiment, a first content stream is received at a receiver device from a transmitter device coupled to the receiver device, wherein the first content stream having media content formatted in a particular package structure, the media content is associated with High-Definition Content Protection (HDCP) values. The first content stream is deciphered into a second content stream by removing the HDCP values from the first content stream, while the package structure of the media content is maintained. | 09-03-2009 |
| 20090222905 | METHOD, APPARATUS, AND SYSTEM FOR PRE-AUTHENTICATION AND PROCESSING OF DATA STREAMS - A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed. | 09-03-2009 |
| 20100146265 | Method, apparatus and system for employing a secure content protection system - A method, apparatus and system for employing a secure content protection system is disclosed. In one embodiment, a certificate having a unique device identification associated with a first device is received, and, at a second device, a revocation list having unauthorized device identifications is received. The unique device identification is incrementally compared with the unauthorized device identifications of the revocation list, and media content is transmitted from the second device to the first device, if the unique device identification is not matched with the unauthorized device identifications of the revocation list. | 06-10-2010 |
| 20100177892 | METHOD, APPARATUS, AND SYSTEM FOR PRE-AUTHENTICATION AND KEEP-AUTHENTICATION OF CONTENT PROTECTED PORTS - A method, apparatus and system for providing pre-authentication and keep-authentication of content protected ports system employing a ratio of one decipher processing engine (e.g., HDCP engine) associated with multiple ports is disclosed is disclosed. In one embodiment, a receiving device is pre-authenticated by a transmitting device, wherein the receiving device to receive a data stream from the transmitting device via a first data path. Further, a first High-Definition Content Protection (HDCP) engine is associated with a first port in the first data path, the first HDCP engine coupled with a second HDCP engine. The second HDCP engine is associated with a plurality of ports in a second data path, each of the plurality of ports associated with a memory pipe having state information relating to each of the plurality of ports, the state information being used to pre-authenticate the receiving device. | 07-15-2010 |
| 20100180115 | METHOD AND SYSTEM FOR DETECTING SUCCESSFUL AUTHENTICATION OF MULTIPLE PORTS IN A TIME-BASED ROVING ARCHITECTURE - In one embodiment of the present invention, a method includes authenticating an HDCP transmitting device at a first port of an HDCP receiving device. A port of the HDCP receiving device is connected to a pipe of an HDCP architecture of the HDCP receiving device at a first time. A synchronization signal is received from the HDCP transmitting device at the port of the HDCP receiving device at a second time. A loss of synchronization between the HDCP transmitting device and the HDCP receiving device is detected when the time-span between the first time and the second time is not greater than the period of time between synchronization signals sent from the HDCP transmitting device. A re-authentication is initiated between the HDCP transmitting device and the HDCP receiving device in response to detecting the loss of synchronization. | 07-15-2010 |
| 20110149032 | TRANSMISSION AND HANDLING OF THREE-DIMENSIONAL VIDEO CONTENT - Embodiments of the invention are generally directed to transmission and handling of three-dimensional video content. An embodiment of a method includes receiving a multimedia data stream including video data utilizing an interface protocol and determining that the received video data includes three-dimensional (3D) video data, where each frame of the video data includes a first vertical synchronization (Vsync) signal prior to an active data region, the active data region including a first data region and a second data region. The method further includes converting the 3D video data from a 3D data format to a two-dimensional (2D) video format, where converting the 3D video data includes identifying a region between the first data region and the second data region, inserting a second Vsync signal between the first data region and the second data region, and providing an identifier to distinguish between the first data region and the second data region. | 06-23-2011 |
| 20110157473 | METHOD, APPARATUS, AND SYSTEM FOR SIMULTANEOUSLY PREVIEWING CONTENTS FROM MULTIPLE PROTECTED SOURCES - A method, apparatus and system for simultaneously previewing contents from multiple protected sources. A primary data stream associated with a primary port is generated, the primary data stream having a primary image to be displayed on a display screen. A secondary data stream is generated associated with a plurality of secondary ports coupled with the primary port, the secondary data stream having a plurality of secondary images received from the plurality of secondary ports. The secondary data stream and the primary data stream are merged into a display data stream, the display data stream having the primary image and further having the plurality of secondary images as a plurality of preview images. The primary image and the plurality of preview images are displayed on the display screen, wherein each of the plurality of preview images is displayed through an inset screen on the display screen. | 06-30-2011 |
| 20110170011 | TRANSMISSION AND DETECTION OF MULTI-CHANNEL SIGNALS IN REDUCED CHANNEL FORMAT - Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency. | 07-14-2011 |
| 20110310301 | MECHANISM FOR MEMORY REDUCTION IN PICTURE-IN-PICTURE VIDEO GENERATION - A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video. | 12-22-2011 |
| 20120092450 | COMBINING VIDEO DATA STREAMS OF DIFFERING DIMENSIONALITY FOR CONCURRENT DISPLAY - Embodiments of the invention are generally directed to combining video data streams of differing dimensionality for concurrent display. An embodiment of an apparatus includes an interface to receive multiple video data streams, a dimensionality of each video stream being either two-dimensional (2D) or three-dimensional (3D). The apparatus further includes a processing module to process a first video data stream as a main video image and one or more video data streams as video sub-images, the processing module including a video combiner to combine the main video data stream and the sub-video data streams to generate a combined video output. The processing module is configured to modify a dimensionality of each of the video sub-images to match a dimensionality of the main video image. | 04-19-2012 |
| 20120147271 | MULTIMEDIA I/O SYSTEM ARCHITECTURE FOR ADVANCED DIGITAL TELEVISION - Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip. | 06-14-2012 |
| 20120182473 | MECHANISM FOR CLOCK RECOVERY FOR STREAMING CONTENT BEING COMMUNICATED OVER A PACKETIZED COMMUNICATION NETWORK - A mechanism for facilitating clock recovery for streaming content over a packetized network is described. A method of embodiments includes receiving an estimated data stream at a first device. The estimated data stream may include estimated data format information relating to a data stream expected to be received at the first device. The method may further include performing, at the first device, clock regeneration of the estimated data stream based on the estimated data format information. The clock regeneration may include performing clock recovery of the estimated data stream. | 07-19-2012 |
| 20120188444 | CONVERSION AND PROCESSING OF DEEP COLOR VIDEO IN A SINGLE CLOCK DOMAIN - Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data. | 07-26-2012 |
| 20120257699 | ADJUSTMENT OF CLOCK SIGNALS REGENERATED FROM A DATA STREAM - Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time. | 10-11-2012 |
| 20120287344 | AUDIO AND VIDEO DATA MULTIPLEXING FOR MULTIMEDIA STREAM SWITCH - Embodiments of the invention describe a multimedia stream switch capable of multiplexing the audio and the video data of a multimedia stream separately. The multiplexing features of embodiments of the invention enable a multimedia stream switch to control each multimedia data type separately instead of multiplexing the whole streams (i.e., multiplexing sets of audio/video data together). Furthermore, prior art multimedia stream switches need to regenerate audio clocks by using phase locked loop (PLL) circuitry which incurs manufacturing and development costs. Embodiments of the invention provide the mixing of audio and video data from different sources without the need for PLL circuitry. | 11-15-2012 |
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| 20080252666 | DISPLAY APPARATUS AND METHOD FOR ADJUSTING BRIGHTNESS THEREOF - A display apparatus and a method for adjusting brightness thereof are provided. The display apparatus includes a panel unit which displays a video signal, a light emitting unit which provides the panel unit with a ray of light and causes the video signal to be visualized, a light emission control unit which controls the light emitting unit so that the ray of light is provided to each of local areas of the panel unit, and a panel control unit which compensates pixels of the video signal in each of local areas, to remove an artifact which is generated due to the ray of light provided to local areas of the panel unit. Because brightness of a screen is adjusted in each of local areas, contrast ratio is enhanced, and improved image quality is provided. | 10-16-2008 |
| 20090141049 | DISPLAY APPARATUS FOR COMPENSATING OPTICAL PARAMETER USING FORWARD VOLTAGE OF LED AND METHOD THEREOF - A display apparatus for compensating an optical parameter, and a display method thereof are disclosed, the display apparatus including a display, an optical source unit, a voltage detection unit which measures the forward voltage of an optical source, and a control unit which controls driving of the optical source unit using a forward voltage of the at least one optical source. Accordingly, the variation of optical parameter is accurately compensated, and the cost for fabricating a temperature sensor and the time for measuring the temperature are reduced. | 06-04-2009 |
| 20110116218 | DISPLAY APPARATUS - Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit. | 05-19-2011 |
| 20110148869 | DISPLAY APPARATUS - A display apparatus in which a user can view a 3D image using shutter glasses is provided. The display apparatus, in which a user can view a three-dimensional (3D) image using shutter glasses, may include: a cover; a display module which is disposed in the cover and displays an image; and a transmitter which is disposed in the cover and transmits a synchronization signal to the shutter glasses to synchronize the image displayed by the display module with the shutter glasses. | 06-23-2011 |
| 20110164401 | BACKLIGHT APPARATUS AND DISPLAY APPARATUS INCLUDING THE SAME - A backlight apparatus includes a substrate which includes a plurality of layers. A plurality of light emitting modules are arranged on a top layer of the plurality of layers closest to a light guide panel, and a plurality of wires penetrates through the plurality of layers to electrically connect the light emitting modules and a plurality of driving units. Accordingly, the width of the substrate of an edge type backlight apparatus which can provide local dimming is reduced. Therefore, the display apparatus using the edge type backlight apparatus can be slim even if it is designed to provide local dimming. | 07-07-2011 |
| 20110248969 | LCD DISPLAY APPARATUS AND LCD DRIVING METHOD - A liquid crystal display (LCD) apparatus and an LCD driving method are provided. The LCD apparatus drives an LCD module by applying temperature compensation to change driving timing according to temperature of the LCD module. Accordingly, the LCD apparatus may reduce a cross-talk occurrence rate in low temperature. | 10-13-2011 |
| 20120268449 | DISPLAY APPARATUS - Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit. | 10-25-2012 |
