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Hoo-Sung Cho
Hoo-Sung Cho, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090278189 | SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME - A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral circuit region disposed on the semiconductor substrate and comprising a peripheral gate pattern, and a resistor disposed in the peripheral circuit region at level above the semiconductor substrate similar to that of the cell semiconductor pattern. | 11-12-2009 |
| 20090315187 | Semiconductor device - A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole. | 12-24-2009 |
| 20100001337 | Semiconductor memory device - A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor. | 01-07-2010 |
| 20100195375 | FULL CMOS SRAM - A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors. | 08-05-2010 |
Hoo-Sung Cho, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100190303 | Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. | 07-29-2010 |
| 20110156159 | Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. | 06-30-2011 |
Hoo-Sung Cho, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090233405 | METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES - Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source. | 09-17-2009 |
| 20090294821 | SEMICONDUCTOR DEVICE HAVING DRIVING TRANSISTORS - One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion. | 12-03-2009 |