| Patent application number | Description | Published |
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| 20080215276 | IN-LINE OVERLAY MEASUREMENT USING CHARGED PARTICLE BEAM SYSTEM - A method and system for controlling an overlay shift on an integrated circuit is disclosed. The method and system comprises utilizing a scanning electron microscope (SEM) to measure the overlay shift between a first mask and a second mask of the circuit after a second mask and comparing the overlay shift to information about the integrated circuit in a database. The method and system includes providing a control mechanism to analyze the overlay shift and feed forward to the fabrication process before a third mask for error correction. | 09-04-2008 |
| 20080265251 | STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas. | 10-30-2008 |
| 20080267489 | METHOD FOR DETERMINING ABNORMAL CHARACTERISTICS IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - A method for determining abnormal characteristics in integrated circuit manufacturing process is disclosed. The method comprises obtaining a charged particle microscope image of a sample test structure, wherein the sample including a reference pattern and a test pattern; measuring gray levels of the reference pattern and the test pattern; calculating a standard deviation from a distribution of the gray levels of the reference pattern measured; and determining the abnormal characteristics of the test pattern based on the gray levels measured and the standard deviation. | 10-30-2008 |
| 20090317958 | METHOD FOR FORMING MEMRISTOR MATERIAL AND ELECTRODE STRUCTURE WITH MEMRISTANCE - Ion Implantation is used to form the memristor material and electrode structure with memristance. First, numerous electron-rich element atoms are implanted into a layer made of transition metal or non-metal. Then, a treating process (such as annealing) is proceeded to expel some electron-rich element atoms away the layer. After that, some electron-rich element vacancy rich regions are formed inside the layer, and then a memristor material is formed. Significantly, the usage of ion implantation can precisely control and flexibly adjust the distribution of the implanted atoms, and then both the amount and distribution of these depleted regions can be effectively adjusted. Hence, the quality of the memristor material is improved. | 12-24-2009 |
| 20100078554 | Structure and Method for Determining a Defect in Integrated Circuit Manufacturing Process - The present invention discloses a structure and a method for determining a defect in integrated circuit manufacturing process. Test keys are designed for the structure to be the interlaced arrays of grounded and floating conductive cylinders, and the microscopic image can be predicted to be an interlaced pattern of bright voltage contrast (BVC) and dark voltage contrast (DVC) signals for a charged particle beam imaging system. The system can detect the defects by comparing patterns of the detected VC signals and the predicted VC signals. | 04-01-2010 |
| 20100102316 | TEST STRUCTURE FOR CHARGED PARTICLE BEAM INSPECTION AND METHOD FOR FABRICATING THE SAME - A test structure and a method for fabricating the same are disclosed. The test structure includes a plurality of sampling lines over a substrate located between a plurality of a first grounding lines and a plurality of a second grounding lines. The sampling lines are selectively electrically coupled to the first grounding line or the second grounding line and include at least one programmed defect. A double-patterning fabricating approach is utilized to produce such test structure which may be applied to a charged particle beam such as an electron-beam defect inspection system. | 04-29-2010 |
| 20100140498 | OPERATION STAGE FOR WAFER EDGE INSPECTION AND REVIEW - The present invention relates to an operation stage of a charged particle beam apparatus which is employed in a scanning electron microscope for substrate (wafer) edge and backside defect inspection or defect review. However, it would be recognized that the invention has a much broader range of applicability. A system and method in accordance with the present invention provides an operation stage for substrate edge inspection or review. The inspection region includes top near edge, to bevel, apex, and bottom bevel. The operation stage includes a supporting stand, a z-stage, an X-Y stage, an electrostatic chuck, a pendulum stage and a rotation track. The pendulum stage mount with the electrostatic chuck has the ability to swing from 0° to 180° while performing substrate top bevel, apex and bottom bevel inspection or review. In order to keep the substrate in focus and avoid a large position shift during altering the substrate observation angle by rotation the pendulum stage, one embodiment of the present invention discloses a method such that the rotation axis of the pendulum stage consist of the tangent of upper edge of the substrate to be inspected. The electrostatic chuck of the present invention has a diameter smaller than which of the substrate to be inspected. During the inspection process the substrate on the electrostatic chuck may be rotated about the central axis on the electrostatic chuck to a desired position, this design insures all position on the bevel and apex are able to be inspected. | 06-10-2010 |
| 20100155596 | METHOD AND SYSTEM FOR HEATING SUBSTRATE IN VACUUM ENVIRONMENT AND METHOD AND SYSTEM FOR IDENTIFYING DEFECTS ON SUBSTRATE - A method for heating a substrate in a vacuum environment and a system therefor is provided. The system includes a chamber capable of holding the substrate located in the vacuum environment and a light source capable of projecting a light beam only on a portion of the substrate. The method includes the following steps. First, the substrate is placed in the vacuumed chamber. Thereafter, the light beam emitted from the light source is projected on the portion of the substrate, such that the portion is significantly heated before whole the substrate is heated. When the light beam is a charged particle beam projected by a charged particle beam assembly and projected on defects located on the substrate, the defects are capable of being identified by an examination result provided by an examination assembly after termination of light beam projection. | 06-24-2010 |
| 20100258720 | TEST STRUCTURE FOR CHARGED PARTICLE BEAM INSPECTION AND METHOD FOR DEFECT DETERMINATION USING THE SAME - A test structure and method thereof for determining a defect in a sample of semiconductor device includes at least one transistor rendered grounded. The grounded transistor is preferably located at at least one end of a test pattern designed to be included in the sample. When the test structure is inspected by charged particle beam inspection, the voltage contrast (VC) of the transistors in the test pattern including the grounded transistor is observed for determination of the presence of defect in the sample. | 10-14-2010 |
| 20100278416 | Method for Inspecting Overlay Shift Defect during Semiconductor Manufacturing and Apparatus Thereof - A method of inspecting for overlay shift defects during semiconductor manufacturing is disclosed. The method can include the steps of providing a charged particle microscopic image of a sample, identifying an inspection pattern period in the charged particle microscopic image, averaging the charged particle microscopic image by using the inspection pattern period to form an averaged inspection pattern period, estimating an average width from the averaged inspection pattern period, and comparing the average width with a predefined threshold value to determine the presence of an overlay shift defect. | 11-04-2010 |
| 20100314539 | METHOD AND APPARATUS FOR IDENTIFYING PLUG-TO-PLUG SHORT FROM A CHARGED PARTICLE MICROSCOPIC IMAGE - A method of inspecting for plug-to-plug short (short circuit) defects on a sample is disclosed. A charged particle beam for imaging the sample is repeatedly line-scanned over the sample with a line-to-line advancement direction perpendicular to the line-scan direction. The method includes scanning the sample with a line-to-line advancement along a first and a second direction, to obtain a first and a second image of the sample, respectively. Then, the method includes identifying plug patterns, represented in the obtained images with abnormal grey levels, as abnormal plug patterns. Next, the method compares the locations of the abnormal plug patterns to determine the presence of plug-to-plug short defects on the sample. | 12-16-2010 |
| 20110013826 | TEST STRUCTURE FOR CHARGED PARTICLE BEAM INSPECTION AND METHOD FOR DEFECT DETERMINATION USING THE SAME - A test structure and method thereof for determining a defect in a sample of semiconductor device includes at least one transistor rendered grounded. The grounded transistor is preferably located at least one end of a test pattern designed to be included in the sample. When the test structure is inspected by charged particle beam inspection, the voltage contrast (VC) of the transistors in the test pattern including the grounded transistor is observed for determination of the presence of defect in the sample. | 01-20-2011 |
| 20110049595 | METHOD FOR FORMING MEMORY CELL TRANSISTOR - A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. The formed memory cell transistor thus comprises a hole structure which is formed from the surface of the top first conductive layer, extending downwards through the first conductive layers and the dielectric layers, and reaching the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure. | 03-03-2011 |
