Patent application number | Description | Published |
20080246067 | Dram device and method of manufacturing the same - In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device. | 10-09-2008 |
20090271982 | Method of forming a wiring having carbon nanotube - In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained. | 11-05-2009 |
20100136226 | Methods of Forming Carbon Nanotubes - Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent. | 06-03-2010 |
20100155853 | MULTIPLEXER AND METHOD OF MANUFACTURING THE SAME - A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address line is arranged on the signal line and includes a plurality of coding lines extending in a second direction different from the first direction and electrically insulated from the data wires. A plurality of switching elements are positioned in the recesses of the data wires and make electrical contact with the coding lines, where the switching element is configured to switch a data signal applied to the data wiring on and off in accordance with a coding signal applied to the coding lines, so that one of the data wires is selected according to a binary code of the address line corresponding to combinations of the coding lines to which coding signal is applied. | 06-24-2010 |
20100208508 | Multi-level nonvolatile memory devices using variable resistive elements - Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto. | 08-19-2010 |
20100289084 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor. | 11-18-2010 |
20110032747 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF PROGRAMMING VARIABLE RESISTANCE MEMORY DEVICES - A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse. | 02-10-2011 |
20120306004 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor. | 12-06-2012 |
20130228870 | SEMICONDUCTOR DEVICE INCLUDING TRENCHES HAVING PARTICULAR STRUCTURES - A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second part of the source/drain of the first region is different from the cross-sectional shape of the second part of the source/drain of the second region. | 09-05-2013 |
20140217483 | SEMICONDUCTOR DEVICES INCLUDING GATE PATTERN, MULTI-CHANNEL ACTIVE PATTERN AND DIFFUSION LAYER - A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described. | 08-07-2014 |
Patent application number | Description | Published |
20090146304 | CARBON NANOTUBE INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATION THEREFOR USING PROTECTED CATALYST LAYERS - A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes. | 06-11-2009 |
20090289322 | MEMORY DEVICES HAVING A CARBON NANOTUBE - In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory. | 11-26-2009 |
20120064692 | METHODS OF MANUFACTURING A MEMORY DEVICE HAVING A CARBON NANOTUBE - A method of manufacturing a memory device having a carbon nanotube can be provided by forming a lower electrode on a substrate and forming an insulating interlayer on the lower electrode. An upper electrode including a diode can be formed on the insulating interlayer, where the upper electrode can have a first void exposing a sidewall of the diode and a portion of the insulating interlayer. A portion of the insulating interlayer can be partially removed to form an insulating interlayer pattern having a second void that exposes a portion of the lower electrode, where the second void can be connected with the first void. A carbon nanotube wiring can be formed from the lower electrode through the second and first voids, where the carbon nanotube wiring may be capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. | 03-15-2012 |
20140375652 | APPARATUS FOR MEASURING STATIC ELECTRICITY AND METHOD FOR MEASURING STATIC ELECTRICITY - An apparatus for measuring static electricity on a substrate includes a measuring unit, an information processing unit, and a display unit. The measuring unit measures first static electricity information from the substrate. The information processing unit calculates a static electricity distribution state of the substrate using the first static electricity information. The display unit displays a graphic image representing the static electricity distribution state. The information processing unit includes a calculating unit and a controller. The calculating unit estimates second static electricity information using the first static electricity information. The controller calculates the static electricity distribution state of the substrate using the first static electricity information and the second static electricity information. | 12-25-2014 |