| Patent application number | Description | Published |
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| 20100195389 | FLASH MEMORY DEVICE AND METHODS PROGRAMMING/READING FLASH MEMORY DEVICE - Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states. | 08-05-2010 |
| 20100223530 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - Provided are a semiconductor memory device and a data processing method thereof. The semiconductor memory device includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data a plurality of memory cells. The memory controller rearranges data by various operations such as a modulation code operation and processes the data according to an ECC operation to reduce the interference between the memory cells. | 09-02-2010 |
| 20100251077 | STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME - A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory. | 09-30-2010 |
| 20100296350 | METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS - A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states. | 11-25-2010 |
| 20100302850 | Storage device and method for reading the same - The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution. | 12-02-2010 |
| 20110032758 | NONVOLATILE MEMORY DEVICE OUTPUTTING ANALOG SIGNAL AND MEMORY SYSTEM HAVING THE SAME - A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation on the binary data. The error correction operation uses a soft decision algorithm. | 02-10-2011 |
| 20110093765 | FLASH MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol. | 04-21-2011 |
| Patent application number | Description | Published |
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| 20090072868 | WIDEBAND TRACK-AND-HOLD AMPLIFIER - A wideband track-and-hold amplifier is provided. The wideband track-and-hold amplifier is provided in front of an analog-to-digital converter, receives and samples an analog signal, and transfers the sampled signal to the analog-to-digital converter, wherein an output load unit having an inductance component is connected to an input terminal of the analog-to-digital converter. Therefore, it is possible to compensate for a high capacitance component of an analog-to-digital converter, to increase the bandwidth of an output signal, and to improve system linearity. | 03-19-2009 |
| 20090073021 | CASCADE COMPARATOR AND CONTROL METHOD THEREOF - A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity. | 03-19-2009 |
| 20090195433 | MULTISTAGE AMPLIFIER AND A METHOD OF SETTLING THE MULTISTAGE AMPLIFIER - A method of settling an amplifier and a multistage amplifier are provided. To settle an amplifier, a plurality of clock signals are, respectively, applied to preset switches, each of which is placed between amplifiers connected in cascade, to open the preset switches sequentially, thereby settling the amplifiers in order. | 08-06-2009 |
| 20100008146 | Memory device and method of programming thereof - The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses. | 01-14-2010 |
| 20100149868 | Access method of non-volatile memory device - Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell. | 06-17-2010 |
| 20100202198 | Semiconductor memory device and data processing method thereof - Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states. | 08-12-2010 |
