| Patent application number | Description | Published |
|---|
| 20080200025 | METHOD OF FORMING COMPOSITE OPENING AND METHOD OF DUAL DAMASCENE PROCESS USING THE SAME - A dual damascene process is provided. A dielectric layer is formed on a substrate and then a via opening is formed in the dielectric layer to expose a liner formed on the substrate. A gap fill (GF) layer is filled into the via opening and a resistant layer is formed on the substrate. A photolithographic process and an etching process are performed to form a trench in the dielectric layer and to remain the gap fill material having a top surface with a convex shape. In the etching process, an etching rate of the gap fill material layer is larger than that of the resistant layer. The gap fill material, the resistant layer, and the liner exposed by the via opening are removed. A conductive layer fills out the trench and the via opening. This invention is focusing on controlling etch-rate to avoid shielding effect when forming the composite opening. | 08-21-2008 |
| 20090023283 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
| 20090023287 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
| 20090259330 | METHOD OF CONTROLLING RESULT PARAMETER OF IC MANUFACTURING PROCEDURE - A method of controlling a result parameter of an IC manufacturing procedure is described. The value of at least one first variable of a process correlated with the result parameter is acquired, and the difference between the predicted value and the target value of the result parameter is calculated from the same using a correlation equation of the first variable and the result parameter. A correcting action is then performed to a subsequent process including at least one second variable correlated with the result parameter, which is based on a correlation equation of the second variable and the result parameter to control the subsequent process and adjust the second variable such that the difference is reduced due to the affect of the second variable to the result parameter. The at least one first variable and the at least one second variable include two or more different physical quantities. | 10-15-2009 |
| 20090314743 | METHOD OF ETCHING A DIELECTRIC LAYER - A method of etching a dielectric layer includes providing a substrate, which includes a dielectric layer and a metal layer, performing a first etching process on the metal layer, and performing a second etching process on the dielectric layer to form a opening in the dielectric layer. The first etching process and the second etching process are in-situ carried out in the same reaction chamber without a vent. Since the first and second etching processes are not performed in different reaction chambers respectively, the cycle time can therefore be improved in the present invention. Because the first and second etching processes are performed without a vent, the substrate is protected from the pollution existing in surrounding. | 12-24-2009 |
| 20100040982 | METHOD FOR FORMING AN OPENING - A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects. | 02-18-2010 |
| 20100227131 | TEST PATTERN STRUCTURE - A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification. | 09-09-2010 |
| 20110021021 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE - A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed. | 01-27-2011 |
