Patent application number | Description | Published |
20110191139 | METHODS AND SYSTEMS FOR DYNAMIC INVENTORY CONTROL - The embodiments of the present invention fill the need of properly controlling product inventory of semiconductor chips by providing methods and systems of dynamic inventory control. The methods and systems timely modify parameters affecting inventory. The parameters may include target inventory, cycle time, wafer start, future inventory and future shipment. In addition, the methods and systems gather real-time customer demand forecast to assist in production planning and adjustment. Further, the methods and systems identify inventory control turning points dynamically to adjust production activities to prevent overstock and to prevent stockout. | 08-04-2011 |
20130117164 | METHODS AND SYSTEMS FOR DYNAMIC INVENTORY CONTROL - A production management system is configured to dynamically control inventory of a semiconductor product to prevent overstock and stockout. The production management system includes a production planning module including components containing data of demand forecast, and customer order. The production management system further includes a dynamic inventory control module including a dynamic inventory control simulation module and an inventory management system, wherein the inventory management system is configured to record real inventory data, and wherein the dynamic inventory control simulation module includes simulators for target inventory, future inventory, future shipment and semiconductor product production. | 05-09-2013 |
20140249884 | SYSTEM FOR DYNAMIC INVENTORY CONTROL - A production management system is configured to dynamically controlling inventory of a semiconductor product to prevent overstock and stockout. The production management system includes a production planning module including components containing data of demand forecast, and customer order. The production management system further includes a dynamic inventory control module including a dynamic inventory control simulation module and an inventory management system, wherein the dynamic inventory control simulation module is configured to adjust a target inventory if a current inventory is beyond a threshold multiplied by the target inventory for M number of review cycles. | 09-04-2014 |
Patent application number | Description | Published |
20090171602 | DEVICE FOR ACCURATELY MEASURING AMPLIFIER'S OPEN-LOOP GAIN WITH DIGITAL STIMULI - A device capable of receiving one or more digital stimulus signals and accurately measuring an open-loop gain of an amplifier comprises: a digital charge converter (DCC), a charge integrator, an A/D converter, a control logic circuit and an arithmetic logic unit (ALU). The DCC and the charge integrator are composed of a plurality of switches, one or more sampling capacitor, at least one integrating capacitor and an operational amplifier under test (OPAUT) with a single-ended output or differential-ended outputs. The DCC, the charge integrator, and the A/D converter are controlled by control signals generated by the logic control circuit and can be reconfigured as a first-order Sigma-Delta modulator capable of receiving at least one of the digital input stimulus signals. The ALU calculates the open-loop gain of the OPAUT with single-ended output or differential-ended outputs according to the digital stimulus signals and the digital output of the first-order Sigma-Delta modulator. | 07-02-2009 |
20140097975 | METHOD FOR ESTIMATING CAPACITANCE WEIGHT ERRORS AND SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER USING THE SAME - A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC. | 04-10-2014 |
20140167988 | DIGITAL-TO-ANALOG CONVERTER (DAC) CIRCUIT AND WEIGHT ERROR ESTIMATION/CALIBRATION METHOD THEREOF - The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory. | 06-19-2014 |
20140347122 | PERIODICALLY RESETTING INTEGRATION ANGLE DEMODULATION DEVICE AND METHOD USING THE SAME - A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties. | 11-27-2014 |
Patent application number | Description | Published |
20080272736 | SMART LEAD ACID BATTERY (DIS)CHARGING MANAGEMENT SYSTEM - A smart lead-acid battery (dis)charging management system comprised of one or a plurality of identical smart battery unit with each including a controller, a lead-acid battery, and a sensor switch device working together with a alternator and a voltage regulator to upgrade charging efficiency, achieve consistent capacity among batteries, and isolate malfunctioning or failing battery to extend service life of the battery. | 11-06-2008 |
20090066291 | DISTRIBUTED ENERGY STORAGE CONTROL SYSTEM - A Distributed Energy Storage Control System (DESCS) comprised of one or a plurality of identical BMS (Battery Management System) battery unit ( | 03-12-2009 |
20110181126 | System and device for current measuring, controlling, and heat sinking - The present invention provides a system and device for current measuring, controlling, and heat sinking which includes a positive electrode terminal carrier, a positive electrode output terminal carrier, a negative electrode terminal carrier, and a current control circuit carrier. The system and device is to be installed on a battery with high current capacity. In which the output current flowing through the battery's positive electrode is measured by the current measurement device which is installed in the positive electrode terminal carrier. A reverse current control switch and a forward current control switch are installed in the current control circuit carrier to control the current flowing path and the current flowing in the path. Furthermore the heat generated by the circuit is radiated by the current control circuit carrier. | 07-28-2011 |
Patent application number | Description | Published |
20080273005 | MIXED COLOR SEQUENTIAL CONTROLLING METHOD AND BACK LIGH MODULE AND DISPLAY DEVICE USING THE SAME - A mixed color controlling method for backlight module and display device using the same, in the method, a mixed color sequential (MCS) algorithm with high contrast enhancement technique is provided in RGB LED backlight display. Owing to synchronous control of LCD panel and LED backlight module, high quality image with suppressed color breakup and motion blur effects is achieved, and display contrast is improved by our novel color sequential technique. In addition, MCS algorithm is useful for color filter-less optical compensated bend (OCB) panel display for alleviating color breakup and motion blur effects. | 11-06-2008 |
20080273006 | COLOR-ZONE LAYOUT OF LIGHT-EMITTING MODULE AND CONTROLLING METHOD OF COLOR SEQUENCE - A color-zone layout of light-emitting module includes at least a light-emitting zone unit. The light-emitting zone unit includes a plurality of blocks, which are divided into a first color-zone, a second color-zone, a third color-zone and a fourth color-zone. A fifth color-zone is located between any two adjacent ones of the color-zones. The five color-zones simultaneously display within a display frame. | 11-06-2008 |
20080284713 | APPARATUS AND METHOD FOR CONTROLLING BACKLIGHT - An apparatus and a method for controlling backlight are provided. The apparatus for controlling backlight is adapted for driving a backlight module of a display panel, and the backlight module includes M luminance-controlling blocks, in which an i | 11-20-2008 |
20090091528 | APPARATUS AND METHOD FOR DYNAMICALLY CONTROLLING BACKLIGHT - An apparatus for dynamically controlling backlight source receives a pixel input data, and outputs a pixel output data and a PWM signal. The apparatus includes image analysis unit for receiving the pixel input data and outputting image data after performing image analysis. An information unit stores relation data including luminance adjusting data and PWM adjusting data corresponding to gray level range. A luminance calculation unit receives the image data from the image analysis unit and the relation data from the information unit, and calculates a required gray level corresponding to a required luminance, and outputs a required pixel luminance data and a required PWM data according to the required gray level. A PWM adjusting unit receives the required PWM data and outputs the PWM signal. A multiplication unit receives the pixel input data and performs luminance adjustment according to the required pixel luminance data for outputting the pixel output data. | 04-09-2009 |
20090185579 | Method and Related Device for Reducing Data Transition in Data Transmission Interface - Reducing data transitions in a data transmission interface includes receiving first data and second data, among which the first data is data being transmitted by the data transmission interface and the second data is next data of the first data in a timing sequence. Corresponding data bits of the first data and the second data are compared to compute how many data bits undergo data transition. If the number of data bits undergoing data transition is greater than half the number of data bits the data transmission interface is capable of transmitting simultaneously, an encoding mode is activated to encode the second data, and an encoding result corresponding to the second data is outputted. | 07-23-2009 |
Patent application number | Description | Published |
20140078129 | LOAD DRIVING APPARATUS AND DRIVING METHOD THEREOF - A load driving apparatus including a first driving unit, a second driving unit, and a circuit switch module is disclosed. The first and the second driving unit are respectively disposed at a first driving channel and a second driving channel and respectively output a first driving signal and a second driving signal for driving a first load and a second load during a channel output period. The circuit switch module is coupled between the first and the second driving channel and includes a plurality of signal transmitting paths. During a data loading period and a charge sharing period, the circuit switch module turns on all the signal transmitting paths, so that a charge sharing effect between the first load and the second load is achieved during the charge sharing period and accordingly the power consumption is reduced. Additionally, a load driving method of the load driving apparatus is disclosed. | 03-20-2014 |
20140253240 | CIRCUIT OF OPERATIONAL AMPLIFIER - A circuit of an operational amplifier includes an operational main circuit, a plurality of current sources, and at least one clamp circuit. The current sources are configured to connect the operational main circuit to a high voltage source or a ground voltage source. The clamp circuit is connected between the operational main circuit and at least one of the current sources. Here, a transistor device connected to the clamp circuit has a crossing-voltage endurance level which is lower than a preset crossing-voltage endurance level of the operational main circuit. | 09-11-2014 |
20160078837 | SOURCE DRIVER, OPERATOIN METHOD THEREOF AND DRIVING CIRCUIT USING THE SAME - A source driver, an operation method thereof and a driving circuit using the same are provided. The source driver includes a gamma voltage generating circuit, a first voltage buffer and a reference voltage driving circuit. The gamma voltage generating circuit receives an inter reference voltage to provide a first gray level reference voltage corresponding to a first display gray level. The first voltage buffer is used for receiving the first gray level reference voltage to provide a driving voltage. The reference voltage driving circuit is coupled to the gamma voltage generating circuit and the first voltage buffer and used for accelerating rising speed or falling speed of the first gray level reference voltage. | 03-17-2016 |
Patent application number | Description | Published |
20150228763 | NON-PLANAR FIELD EFFECT TRANSISTOR HAVING A SEMICONDUCTOR FIN AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. | 08-13-2015 |
20150294914 | Flexible Device Modulation By Oxide Isolation Structure Selective Etching Process - A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device. | 10-15-2015 |
20150340475 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. | 11-26-2015 |
20160071799 | SEMICONDUCTOR STRUCTURE WITH CONTACT PLUG - The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner. | 03-10-2016 |
Patent application number | Description | Published |
20140370696 | MECHANISMS FOR FORMING OXIDE LAYER OVER EXPOSED POLYSILICON DURING A CHEMICAL MECHANICAL POLISHING (CMP) PROCESS - Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation. | 12-18-2014 |
20150099431 | CMP Slurry Particle Breakup - A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range. | 04-09-2015 |
20150187594 | Composite Structure for Gate Level Inter-Layer Dielectric - A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process. | 07-02-2015 |