Patent application number | Description | Published |
20080209119 | METHODS AND SYSTEMS FOR GENERATING ERROR CORRECTION CODES - Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns of the data block, and Y is greater than or equal to 2. A second buffer stores Y partial-parity columns. An encoder is used for encoding the first section read from the first buffer to generate the partial-parity columns, and then storing the partial-parity columns in the second buffer. The second section read from the first buffer and the partial-parity columns read from the second buffer are encoded to generate updated partial-parity columns. Next, the partial-parity columns in the second buffer are updated by storing the updated partial-parity columns. | 08-28-2008 |
20080211529 | INTEGRATED CIRCUIT FOR BEING APPLIED TO ELECTRONIC DEVICE, AND ASSOCIATED TESTING SYSTEM - An integrated circuit (IC) for being applied to an electronic device includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to another IC for testing. A testing system includes at least one testing device and a plurality of ICs that are tested by the testing device. The ICs are coupled to the testing device. Each IC of the ICs is for being applied to an electronic device and includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to one of the other IC(s) for testing. | 09-04-2008 |
20090196131 | SYSTEM AND METHOD FOR PRINTING VISIBLE IMAGE ONTO OPTICAL DISC THROUGH TUNING DRIVING SIGNAL OF OPTICAL PICK-UP UNIT - A system and method for printing a visible image onto an optical disc through tuning a driving signal of an optical pick-up unit are disclosed. The system includes a driving circuit, coupled to the optical pick-up unit, for providing a driving signal to drive the optical pick-up unit; and an adjusting circuit, coupled to the driving circuit, for controlling the driving circuit to adjust the driving signal according to a rotation source signal corresponding to a rotation of the optical disc. | 08-06-2009 |
20090265596 | SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF - An integrated circuit package comprising a semiconductor device and pins is provided. The semiconductor device comprises first and second scan chains, each having an input port and an output port. The semiconductor device further comprises at least two first pads, at least two second pads, and a connecting device. The at least two first pads are coupled to the input port of the first scan chain and the output port of the second scan chain, respectively. The at least two second pads are coupled to the output port of the first scan chain and the input port of the second scan chain, respectively. The connecting device is coupled between the first and the second chains, and is capable of controlling electrical connection between the input port of the second scan chain and the output port of the first scan chain. When the connecting device is disabled, the input port of the second scan chain is electrically disconnected from the output port of the first scan chain. The first pads are electrically connected to the pins and the second pads are not electrically connected to any pins of the integrated circuit package. | 10-22-2009 |
20100077134 | FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE - The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals. | 03-25-2010 |
20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 12-30-2010 |
20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
20100332951 | METHOD FOR PERFORMING COPY BACK OPERATIONS AND FLASH STORAGE DEVICE - The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC data is then decoded without performing error correction to calculate a fail count of the first ECC data. The fail count is then compared with a first threshold value. When the fail count is less than the first threshold value, a first program command is sent to the flash memory for storing the first ECC data to a second address of the flash memory. When the fail count is less than the first threshold value, the first ECC data is not sent back to the flash memory. | 12-30-2010 |
20110119455 | METHODS OF UTILIZING ADDRESS MAPPING TABLE TO MANAGE DATA ACCESS OF STORAGE MEDIUM WITHOUT PHYSICALLY ACCESSING STORAGE MEDIUM AND RELATED STORAGE CONTROLLERS THEREOF - A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium. | 05-19-2011 |
20110286271 | MEMORY SYSTEMS AND METHODS FOR READING DATA STORED IN A MEMORY CELL OF A MEMORY DEVICE - A memory system is provided. A memory device includes multiple memory cells for storing data. A controller is coupled to the memory device for accessing the memory device. When reading the data stored in a memory cell, the controller receives a digital signal representing content of the data stored in the memory cell, and detects a level of a voltage or conducted current of the memory cell according to the digital signal to obtain the content of the data. | 11-24-2011 |