Hong-Ching
Hong-Ching Chen, Fang-Shan City TW
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20100306447 | DATA UPDATING AND RECOVERING METHODS FOR A NON-VOLATILE MEMORY ARRAY - Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions. | 12-02-2010 |
20110010512 | METHOD FOR CONTROLLING STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORY UNITS AND STORAGE SYSTEM USING THE SAME - A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has at least one high priority cycle and at least one low priority cycle. When a low priority cycle is overlapped with a high priority cycle, the low priority cycle is suspended, and the high priority cycle is operated first. After the high priority cycle is finished, the suspended low priority cycle is then resumed. By doing so, the shared I/O bus may be used by one memory unit during a busy cycle for another memory unit, during which the latter memory unit does not use the I/O bus. Therefore, the I/O bus can be more efficiently used. | 01-13-2011 |
20110167323 | Error-Correcting Apparatus and Method Thereof - The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information. | 07-07-2011 |
Hong-Ching Chen, Kao-Hsiung TW
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20090310716 | CHANNEL BIT DETECTION SYSTEM - A channel bit detection system is provided. The channel bit detection system includes an RF front end, an analog-to-digital converter, a combiner, a length estimator, a length accumulator, an offset control, and a channel bit detector. The RF front end receives an RF signal, and is then digitized at a sampling rate R into a plurality of samples by the analog-to-digital converter. The combiner produces combined samples by shifting the plurality of samples an offset value. The length estimator estimates a length of each two consecutive combined samples. The length accumulator produces land lengths and pit lengths of the combined samples according to length of each two consecutive combined samples. The offset control provides the offset value according to the land lengths and the pits lengths. The channel bit detector recovers the channel bit from the plurality of combined samples. | 12-17-2009 |
Hong-Ching Chen, Kao-Hsiung County TW
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20090279636 | CHIP AND SYSTEM UTILIZING THE SAME - A system including a pulse generating module and a processing module is disclosed. The pulse generating module generates a target signal. The processing module outputs a processing signal according to the target signal. Throughput of the target signal exceeds throughput of the processing signal. | 11-12-2009 |
Hong-Ching Chen, Kao-Hsiun Hsien TW
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20080282068 | HOST COMMAND EXECUTION ACCELERATION METHOD AND SYSTEM - The present invention sets forth an interface method and system for host acceleration between an electronic device and a host PC. The system comprises an acceleration unit for rapidly classifying a type of an host command then issuing a flag signal to a microprocessor. The microprocessor then executes corresponding actions according to the flag signal and the host command without parsing the host command for accelerating the data communication between the device and a host PC. | 11-13-2008 |
Hong-Ching Chen, Kao-Hsiung City TW
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20150039823 | TABLE LOOKUP APPARATUS USING CONTENT-ADDRESSABLE MEMORY BASED DEVICE AND RELATED TABLE LOOKUP METHOD THEREOF - A table lookup apparatus has a content-addressable memory (CAM) based device and a first cache. The CAM based device is used to store at least one table. The first cache is coupled to the CAM based device, and used to cache at least one input search key of the CAM based device and at least one corresponding search result. Besides, the table lookup apparatus may further includes a plurality of second caches and an arbiter. Each second cache is used to cache at least one input search key of the CAM based device and at least one corresponding search result. The arbiter is coupled between the first cache and each of the second caches, and used to arbitrate access of the first cache between the second caches. | 02-05-2015 |
20150339253 | ELECTRONIC DEVICE WITH ENHANCED MANAGEMENT DATA INPUT/OUTPUT CONTROL - An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus. | 11-26-2015 |
Hong-Ching Chen, Kaohsiung TW
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20160124863 | Efficient MAC Address Storage For Virtual Machine Applications - Examples of efficient MAC address storage are described, including methods and an apparatus. A method may involve obtaining a plurality of identifications associated with one or more applications executed on a computing apparatus, with each identification of the plurality of identifications different from one another. The method may also involve storing an identification entry representative of the plurality of identifications associated with the one or more applications. The identification entry may require an amount of memory space for storage less than an amount of memory space required to store the plurality of identifications associated with the one or more applications. The plurality of identifications may be a plurality of MAC addresses. The one or more applications may be one or more virtual machines. | 05-05-2016 |