Patent application number | Description | Published |
20090148995 | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) - This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole. | 06-11-2009 |
20100084707 | Polysilicon control etch-back indicator - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 04-08-2010 |
20100099230 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer - This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide. | 04-22-2010 |
20100105182 | Shallow source MOSFET - Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening. | 04-29-2010 |
20100190307 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 07-29-2010 |
20100291744 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 11-18-2010 |
20100314659 | Nanotube Semiconductor Devices - A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation. | 12-16-2010 |
20100317158 | Method for Forming Nanotube Semiconductor Devices - A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure. | 12-16-2010 |
20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 02-17-2011 |
20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 02-17-2011 |
20110068386 | DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS - A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer. | 03-24-2011 |
20110140167 | Nanotube Semiconductor Devices - A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure. | 06-16-2011 |
20110198588 | Polysilicon control etch-back indicator - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 08-18-2011 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-15-2011 |
20120098059 | DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS - A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 04-26-2012 |
20120193631 | POLYSILICON CONTROL ETCH BACK INDICATOR - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 08-02-2012 |
20120205737 | SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 08-16-2012 |
20120292693 | FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE - Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure. | 11-22-2012 |
20130015494 | Nanotube Semiconductor Devices and Nanotube Termination Structures - A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. | 01-17-2013 |
20140042490 | NANOTUBE SEMICONDUCTOR DEVICES - Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer. | 02-13-2014 |
20140073098 | METHOD FOR FORMING A SCHOTTKY BARRIER DIODE INTEGRATED WITH A TRENCH MOSFET - A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode. | 03-13-2014 |
20140091386 | MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region. | 04-03-2014 |
20140299914 | NANOTUBE SEMICONDUCTOR DEVICES - Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer. | 10-09-2014 |