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Honda, Kawasaki
Hirotake Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090243626 | AMPLIFICATION APPARATUS AND AMPLIFIER FAILURE DETECTING METHOD - An amplification apparatus including a plurality of amplifiers includes a carrier amplifier, a peak amplifier including a gate bias circuit including a resistor for supplying a gate bias voltage, a comparator for outputting a resultant signal determined by comparison of a predetermined threshold voltage with a voltage across the resistor included within the gate bias circuit, and a failure detecting circuit for detecting whether a failure in the plurality of amplifiers is caused or not based on the resultant signal. | 10-01-2009 |
| 20100033243 | Amplifying Apparatus - The amplifying apparatus includes an amplifier having a circuit constant determined so as to satisfy a condition for E-class operation; power detecting unit which detects an output electricity from the amplifier; and controlling unit which controls the circuit constant in accordance with the output power detected by the power detecting unit. | 02-11-2010 |
| 20100240329 | AMPLIFYING DEVICE AND TRANSMITTER APPARATUS - An amplifying device includes an amplifier including a first amplifying element with a drain voltage thereof being controlled, and a second amplifying element, the amplifier amplifying a transmission signal with the first and second amplifying elements, synthesizing the transmission signals amplified by the first and second amplifying elements, and outputting the synthesized transmission signal; a distortion compensator part which performs distortion compensation on the input signal in accordance with a compensation coefficient derived from a difference between a input signal and a feedback signal generated from a portion of a signal output from the amplifier; and a controller part which controls the drain voltage of the first amplifying element in response to a result of a comparison between a power level of the input signal prior to the distortion compensation operation by the distortion compensator part and a threshold value. | 09-23-2010 |
| 20110068882 | FILTER AND AMPLIFYING CIRCUIT - There is provided a filter which includes a transmission line, a stub branched from the transmission line, the stub electrically coupled with the transmission line, and a resonator configured to electromagnetically couple with the stub and to resonate at an odd harmonic frequency of a fundamental wave, the fundamental wave propagating through the transmission line. | 03-24-2011 |
Ryoji Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100226321 | Base station apparatus, terminal apparatus, and communication method - A base station apparatus includes a wireless receiving unit wirelessly receiving identification information on a terminal apparatus located in the vicinity of the base station apparatus; a storage unit storing the identification information received by the wireless receiving unit; a request receiving unit receiving, from a communication apparatus, a start request containing identification information regarding a terminal apparatus to be started; a determination unit determining whether the identification information contained in the start request received by the request receiving unit having been stored in the storage unit; and a distribution unit wirelessly distributing a start instruction to start the terminal apparatus indicated by the identification information upon the determination unit determining the identification information having been stored in the storage unit. | 09-09-2010 |
Satofumi Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100329069 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of a row address in a previous cycle and a row address in a current cycle, and a row address decoder that decodes the row address, and outputs a word line select signal to select one of word lines connected to a part of the plurality of memory cells based on the decoded row address, and prevents the output of the word line select signal when the control signal outputted from the comparator is inputted to the row address decoder. | 12-30-2010 |
| 20110019490 | SEMICONDUCTOR MEMORY - A semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a lager area size than the other memory cells, the plurality of memory cells and at least one of the redundant memory cells arrayed on at least one of the row lines. | 01-27-2011 |
Takuya Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090327164 | LOAD DISTRIBUTING METHOD, COMPUTER PRODUCT, AND LOAD DISTRIBUTING APPARATUS - A load distributing method includes receiving information concerning resources of a terminal device from the terminal device in a grid on a network of a grid computing system; extracting, from a computation data group related to grid computing and based on the received information concerning resources, computation data corresponding to the resources; and distributing to the terminal device, the extracted computation data together with content reproducible during processing of the computation data. | 12-31-2009 |
Toshiki Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090290871 | SIGNAL-LIGHT IDENTIFYING APPARATUS, WDM TRANSCEIVER, AND METHOD OF IDENTIFYING SIGNAL LIGHT - Spectral components of input signal light is partially removed by allowing the input signal light regulated to predetermined power to pass through an optical filter, and the rate of the input signal light is identified in response to the power of the signal light passing through the optical filter. | 11-26-2009 |
Toshiyuki Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090166784 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Gold bumps are located over electrode pads of a solid imaging device and an adhesive is formed over the gold bumps. A transparent plate is supported by the gold bumps and is made to adhere over the solid imaging device by the adhesive. The gold bumps and an electrode and wiring pattern formed over a circuit board are connected by gold wires. At this time the gold wires are approximately parallel to the circuit board near portions where the gold wires and the gold bumps are connected. As a result, it is easy to locate the transparent plate over the portions where the gold wires and the gold bumps are connected. By locating the adhesive over the portions where the gold wires and the gold bumps are connected, the solid imaging device can be made small and light. As a result, a smaller lighter semiconductor device is fabricated. | 07-02-2009 |
| 20100052212 | METHOD OF RESIN SEALING ELECTRONIC PART - A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by the upper mold into the molten resin so that the resin sealing is achieved. The resin material is received in the cavity forming part of the lower mold after the resin material is pressurized and dispersed in a sealing resin supply apparatus. | 03-04-2010 |
Yasufumi Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100023827 | SOFT ERROR CORRECTION METHOD, MEMORY CONTROL APPARATUS AND MEMORY SYSTEM - A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address. | 01-28-2010 |
Yoshinori Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20110231364 | ID MANAGEMENT METHOD, ID MANAGEMENT SYSTEM, AND COMPUTER-READABLE RECORDING MEDIUM - Provided is an information processing apparatus | 09-22-2011 |
Yuri Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100219874 | LEVEL SHIFT CIRCUIT AND SWITCHING CIRCUIT INCLUDING THE SAME - The level shift circuit that converts a level of an input signal into a level between a first and a second voltage, which is higher than the first voltage includes a select circuit that generates an oscillation signal, where at least a frequency or an amplitude of the oscillation signal changes according to an input signal, a filter circuit that removes a DC component of the oscillation signal output from the select circuit and outputs an AC component, a detect circuit that operates between the first voltage and an output side voltage of the filter circuit, and generates a control signal including a signal voltage that changes according to at least a frequency or an amplitude of the AC component of the oscillation signal, and an output circuit that generates an output signal having a level between the first voltage and the second voltage according to the control signal. | 09-02-2010 |
Yusuke Honda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100142541 | COMMUNICATION SYSTEM - A media gateway is configured to include a subscriber loop interface circuit, and TDM data-IP packet convert modules # | 06-10-2010 |
| 20100158008 | SWITCHING EXCHANGE - In a network system where a switching exchange accommodating an ISDN provides TDMoIP packet communication over an IP network, measures for packet loss prevention need to be taken during a period during which a TDM service is packet-transferred over the IP network. When a transmitting-end switching exchange in the above network system multiplexes TDM data, the present invention varies the degree of multiplicity in accordance with the delay in the IP network and the type of data. | 06-24-2010 |