| Patent application number | Description | Published |
|---|
| 20090108376 | SEMICONDUCTOR DEVICE HAVING MOS TRANSISTORS WHICH ARE SERIALLY CONNECTED VIA CONTACTS AND CONDUCTION LAYER - A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes. | 04-30-2009 |
| 20100078726 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor diffusion region of a first transistor, a second semiconductor diffusion region of a second transistor, and a third semiconductor diffusion region that connects the first and second semiconductor diffusion regions to each other. | 04-01-2010 |
| 20110085397 | Semiconductor device and information processing system including the same - A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change. | 04-14-2011 |
| 20110087835 | Semiconductor memory device and data processing system - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 04-14-2011 |
