| Patent application number | Description | Published |
|---|
| 20090195310 | LNA HAVING A POST-DISTORTION MODE AND A HIGH-GAIN MODE - A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA. | 08-06-2009 |
| 20100029223 | METHODS AND APPARATUS FOR IMPLEMENTING PHASE ROTATION AT BASEBAND FREQUENCY FOR TRANSMIT DIVERSITY - An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path may perform phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal. | 02-04-2010 |
| 20100029323 | SYSTEMS AND METHODS FOR ADJUSTING THE GAIN OF A RECEIVER THROUGH A GAIN TUNING NETWORK - A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network. | 02-04-2010 |
| 20100289537 | SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON - An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage. | 11-18-2010 |
| 20100328127 | INTERFERENCE REDUCTION USING VARIABLE DIGITAL-TO-ANALOG CONVERTER (DAC) SAMPLING RATES - A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC. | 12-30-2010 |
| 20110105070 | Direct conversion receiver architecture - A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. | 05-05-2011 |
