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Hoivik
Nils D. Hoivik, Billingstad NO
| Patent application number | Description | Published |
|---|---|---|
| 20090016028 | METHOD OF OBTAINING ENHANCED LOCALIZED THERMAL INTERFACE REGIONS BY PARTICLE STACKING - Integrated circuit-chip hot spot temperatures are reduced by providing localized regions of higher thermal conductivity in the conductive material interface at pre-designed locations by controlling how particles in the thermal paste stack- or pile-up during the pressing or squeezing of excess material from the interface. Nested channels are used to efficiently decrease the thermal resistance in the interface, by both allowing for the thermally conductive material with a higher particle volumetric fill to be used and by creating localized regions of densely packed particles between two surfaces. | 01-15-2009 |
| 20090258455 | METHOD OF MINIMIZING BEAM BENDING OF MEMS DEVICE BY REDUCING THE INTERFACIAL BONDING STRENGTH BETWEEN SACRIFICIAL LAYER AND MEMS STRUCTURE - The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure. | 10-15-2009 |
Nils D. Hoivik, Pleasantville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080277769 | Package Integrated Soft Magnetic Film for Improvement In On-Chip Inductor Performance - An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit. | 11-13-2008 |
Nils Deneke Hoivik, Pleasantville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090001587 | Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION - Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor. | 01-01-2009 |