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Hoefler, TX

Alexander Hoefler, Austin, TX US

Patent application numberDescriptionPublished
20090219747METHOD OF PROGRAMMING A MEMORY HAVING ELECTRICALLY PROGRAMMABLE FUSES - An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse.09-03-2009
20100181629METHOD OF FORMING AN INTEGRATED CIRCUIT - A method includes forming a source, a drain, and a disposable gate (07-22-2010

Alexander B. Hoefler, Austin, TX US

Patent application numberDescriptionPublished
20080212387INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.09-04-2008
20080212388INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.09-04-2008
20080265962SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD - A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.10-30-2008
20080266994LEVEL DETECT CIRCUIT - A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.10-30-2008
20100061162CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING - A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.03-11-2010
20100198896RANDOM NUMBER GENERATOR - A random number generator includes a first one time programmable (OTP) element and a second OTP element. The first OTP element and second OTP element have a first distribution of probable values for an electrical characteristic when unprogrammed and a second distribution of probable values when programmed. A programming circuit applies a programming signal to the first OTP element and to the second OTP element that causes the first OTP element to switch from being unprogrammed to being programmed and having a first value for its electrical characteristic and the second OTP element to switch from being unprogrammed to being programmed and having a second value for its electrical characteristic. A sense amplifier provides an output signal at a first logic state when the first value exceeds the second value and at a second logic state when the second value exceeds the first value.08-05-2010

Patent applications by Alexander B. Hoefler, Austin, TX US