Patent application number | Description | Published |
20100052646 | CURRENT MIRROR WITH IMMUNITY FOR THE VARIATION OF THRESHOLD VOLTAGE AND THE GENERATION METHOD THEREOF - A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current. | 03-04-2010 |
20100329052 | Word line defect detecting device and method thereof - Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line. | 12-30-2010 |
20120215960 | DEVICE FOR INCREASING CHIP TESTING EFFICIENCY AND METHOD THEREOF - A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result. | 08-23-2012 |
20140022858 | METHOD OF CONTROLLING A REFRESH OPERATION OF PSRAM AND RELATED DEVICE - A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a PSRAM is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration. The first refresh request is delayed if the first refresh request conflicts with an external command of the PSRAM. | 01-23-2014 |
20140043888 | METHOD OF OPERATING PSRAM AND RELATED MEMORY DEVICE - The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency. | 02-13-2014 |
20140043922 | METHOD OF PROVIDING WRITE RECOVERY PROTECTION IN PSRAM AND RELATED DEVICE - A method of operating a PSRAM includes selecting a bit on a word line of the PSRAM, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends. | 02-13-2014 |
20140050038 | MEMORY DEVICE WITH BI-DIRECTIONAL TRACKING OF TIMING CONSTRAINTS - A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line. | 02-20-2014 |