| Patent application number | Description | Published |
|---|
| 20100027315 | Resistive memory device and writing method thereof - A resistive memory device operates to sequentially activate bit lines, which are divided into plural groups, after precharging all of word and bit lines in a writing operation. The device is able to write a large amount of data therein at a high frequency, with a reduced the chip size. | 02-04-2010 |
| 20100027326 | Memory device, memory system having the same, and programming method of a memory cell - A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit. | 02-04-2010 |
| 20100085826 | Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same - The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit. | 04-08-2010 |
| 20100091552 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit. | 04-15-2010 |
| 20100172172 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND VOLTAGE SUPPLY METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices. | 07-08-2010 |
| 20100172174 | SEMICONDUCTOR DEVICE HAVING ARCHITECTURE FOR REDUCING AREA AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation. | 07-08-2010 |
| 20100182866 | SEMICONDUCTOR MEMORY DEVICE FOR COMPENSATING FOR OPERATING VOLTAGE DIFFERENCE BETWEEN NEAR CELL AND FAR CELL IN CONSIDERATION OF CELL POSITION, AND MEMORY CARD AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into at least two local bit line groups arranged to be alternately connected with at least two global bit lines and coupled with the memory cells; a plurality of bit line selection drivers respectively connected to the local bit lines; an internal boosted voltage generator configured to generate at least two internal boosted voltages having different levels; and a power transmitter configured to respectively transmit the at least two internal boosted voltages to at least two bit line selection driver groups, into which the plurality of bit line selection drivers are classified according to arrangement of the local bit lines. Accordingly, repair efficiency can be increased and near-far compensation can be more correctly performed. | 07-22-2010 |
| 20100202182 | MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS - A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays. | 08-12-2010 |
| 20100208381 | Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal. | 08-19-2010 |
| 20100208504 | Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains. | 08-19-2010 |
| 20100214819 | RESISTIVE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF CONTROLLING INPUT AND OUTPUT OPERATIONS OF THE SAME - A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage | 08-26-2010 |
| 20100214831 | Memory device, memory system having the same, and programming method of a memory cell - A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data. | 08-26-2010 |
| 20100214862 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 08-26-2010 |
| 20100218073 | Resistive Memory Devices and Methods of Controlling Operations of the Same - To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc. | 08-26-2010 |
| 20100220513 | Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data - A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided. | 09-02-2010 |
| 20100223532 | SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE - A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit. | 09-02-2010 |
| 20100226165 | RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF - A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode. | 09-09-2010 |
| 20100246234 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers. | 09-30-2010 |
| 20100246246 | Memory device, memory system having the same, and programming method of a memory cell - A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell. | 09-30-2010 |
| 20100250848 | APPARATUSES AND METHODS PROVIDING REDUNDANT ARRAY OF INDEPENDENT DISKS ACCESS TO NON-VOLATILE MEMORY CHIPS - A controller may include a RAID controller and an access controller. The RAID controller exchanges data with a host and select ones of a plurality of RAID levels responsive to RAID level information. The access controller is connected to the RAID controller and to a plurality of channels that are each connected to a plurality of non-volatile memory chips. The access controller accesses data in at least one of the non-volatile memory chips connected to each of the channels according to the selected RAID level. The controller may alternatively or additionally include a storage device and a main processor. The main processor is configured to logically partition a plurality of non-volatile memory chips that are connected to each of a plurality of channels into a normal partition region and a RAID level partition region, where data access is performed according to a selected RAID level, in response partition information that is stored in the storage device. | 09-30-2010 |
| 20100284209 | INTEGRATED CIRCUIT MEMORY SYSTEMS AND PROGRAM METHODS THEREOF INCLUDING A MAGNETIC TRACK MEMORY ARRAY USING MAGNETIC DOMAIN WALL MOVEMENT - Provided are nonvolatile memory devices and program methods thereof. an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track. | 11-11-2010 |
| 20100284216 | INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME - An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data. | 11-11-2010 |
| 20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 12-09-2010 |
| 20110062448 | Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices - Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer. | 03-17-2011 |
| 20110063885 | Information storage devices including vertical nano wires - A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires. | 03-17-2011 |
| 20110085368 | Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines. | 04-14-2011 |
| 20110108704 | Image sensors and methods of operating the same - Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively. | 05-12-2011 |
| 20110128772 | Nonvolatile memory cells and nonvolatile memory devices including the same - A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor. | 06-02-2011 |
| 20110133778 | NON-VOLATILE LOGIC CIRCUITS, INTEGRATED CIRCUITS INCLUDING THE NON-VOLATILE LOGIC CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS - Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different. | 06-09-2011 |
