| Patent application number | Description | Published |
|---|
| 20080230912 | WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern. | 09-25-2008 |
| 20080230923 | CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE - A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes. | 09-25-2008 |
| 20090008790 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole. | 01-08-2009 |
| 20090085224 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced. | 04-02-2009 |
| 20090128662 | Apparatus and method for processing image - Provided are an image signal processing apparatus and method. According to the image signal processing method, by simultaneously performing in an integrated manner image denoising and interpolation using 4-directional image gradient information which defines differences in color brightness between adjacent pixels on the basis of edge direction information obtained from a bayer image output from an image sensor, it is possible to improve picture quality and processing speed. | 05-21-2009 |
| 20090186446 | Semiconductor device packages and methods of fabricating the same - Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material. | 07-23-2009 |
| 20090261474 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 10-22-2009 |
| 20090305502 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 12-10-2009 |
| 20100086229 | Image signal processing apparatus and method - An image signal processing method. A first coefficient indicating a probability that a first pixel of an input image is an edge may be calculated. A first edge enhanced signal where an edge of the input image is enhanced may be multiplied with the first coefficient, and a first low-pass filtered signal where the input image is low-pass filtered may be multiplied with a second coefficient indicating a probability that the first pixel is not an edge. The two calculated values may be added, and thus an edge enhanced signal may be generated. | 04-08-2010 |
| 20100090338 | MICROELECTRONIC DEVICES INCLUDING MULTIPLE THROUGH-SILICON VIA STRUCTURES ON A CONDUCTIVE PAD AND METHODS OF FABRICATING THE SAME - A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed. | 04-15-2010 |
| 20100091176 | System and method for automatic exposure - Disclosed are an auto exposure system and a method thereof. The auto exposure system may check whether an exposure target value is correct using brightness information of an input image. When the exposure target value is not proper, the auto exposure system may readjust the exposure target value through analyzing the brightness information of the input image. Also, the auto exposure system may correct exposure of the input image based on an exposure correction value according to the adjusted exposure target value, thereby adjusting the exposure of the input image to be proper. Also, exposure information of the input image may be easily obtained from a final exposure target value. | 04-15-2010 |
| 20100105169 | SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another. | 04-29-2010 |
| 20100142847 | Apparatus and method for enhancing image base on luminance information of pixel - An image enhancement apparatus and method based on luminance information of a pixel. The image enhancement apparatus may determine luminance data of each of a plurality of pixels, and may adaptively determine a conversion ratio according to the luminance data to apply the conversion ratio to an input image, thereby performing image-enhancing. The image enhancement apparatus may adaptively converse the input image according to luminance data, thereby precisely and effectively performing image-enhancing. | 06-10-2010 |
| 20100149373 | Apparatus and method of reproducing color - A color reproduction apparatus may include a white balance performing unit to perform white balance with respect to an image obtained from a sensor using a white balance gain, an image restoring unit to restore an RGB image from the white-balanced image by interpolating a color filter array image, a first color corrector to correct a color distortion caused by a light source by applying first correction data, and a second color corrector to correct a color distortion caused by a characteristic of a sensor by applying second correction data. | 06-17-2010 |
| 20100150439 | Apparatus and method for adjusting auto white balance using effective area - An apparatus and method for auto white balance adjusting using an effective area. The auto white balance adjusting apparatus may extract a grey area from an input image, and select an effective area from the grey area according to color temperature and luminance, thereby performing white balance using the effective area. The auto white balance adjusting apparatus may perform white balance of the input image using image information of the effective area which is a more precise grey area, thereby improving the white balance. | 06-17-2010 |
| 20100285635 | CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE - A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes. | 11-11-2010 |
| 20100327422 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME, AND STACK MODULE AND MEMORY CARD INCLUDING THE SAME - A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided. | 12-30-2010 |
| 20110026819 | Apparatus, method, and medium of encoding and decoding image data using sampling - An image data encoding/decoding apparatus and method using sampling is provided. The image data encoding apparatus may compress image data, pre-processed for each block, after sampling or without sampling, and select a more efficient compression mode from results of the compressing. The image data decoding apparatus may determine a decompression mode corresponding to the selected compression mode, and up-sample the image data after decompressing the image data based on a decompression mode, or decompress the image data without sampling, to provide high definition regardless of a type of image data. | 02-03-2011 |
| 20110031621 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 02-10-2011 |
| 20110050948 | APPARATUS AND METHOD FOR ADJUSTING AUTOMATIC WHITE BALANCE BY DETECTING EFFECTIVE AREA - An automatic white balance adjusting apparatus and method based on detection of an effective area. The automatic white balance adjusting apparatus may detect the effective area by using a color temperature, a luminance, and a correlation, and may adjust a white balance with respect to the detected effective area. | 03-03-2011 |
| 20110086486 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 04-14-2011 |
| 20110091100 | Apparatus and method of removing false color in image - An image processing method and apparatus is provided, with which a size of a filter window may be decreased by determining an edge direction of each of the pixels constituting an image and by vertically applying an anisotropic filter window to the determined edge direction. | 04-21-2011 |
| 20110097846 | SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug. | 04-28-2011 |
| 20110116714 | Image interpolation method and apparatus using reference block based on direction - Provided is an image interpolation method and apparatus using a reference block depending on a direction. The image interpolation method may generate a horizontal reference block and a vertical reference block each with respect to an inputted image, and determine interpolation directivity with respect to the inputted image using the generated horizontal reference block and vertical reference block, thereby performing an interpolation on an image based on accurate interpolation directivity. In particular, the image interpolation method may determine whether to verify interpolation directivity depending on an edge intensity of an inputted image, thereby performing a color filter array (CFA) interpolation on an image based on an edge direction without determining the interpolation directivity, when the edge intensity is strong. | 05-19-2011 |
| 20110147946 | WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern. | 06-23-2011 |
| 20110164833 | Image processing apparatus and method - An image processing apparatus is provided. The image processing apparatus for image signal processor (ISP) realization may include a Static Random Access Memory (SRAM) for each function module. A unified SRAM to store at least one line data of an input image for each of a plurality of functions modules within the image processing apparatus is further provided. | 07-07-2011 |
